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M
Devices included:
* PIC16C72 * PIC16CR72
PIC16C72 SERIES
Pin Diagrams
SDIP, SOIC, SSOP, Windowed Side Brazed Ceramic
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL *1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA
8-Bit CMOS Microcontrollers with A/D Converter
Microcontroller Core Features:
* High-performance RISC CPU * Only 35 single word instructions to learn * All single cycle instructions except for program branches which are two cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM) * Interrupt capability * Eight level deep hardware stack * Direct, indirect, and relative addressing modes * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Selectable oscillator options * Low-power, high-speed CMOS technology * Fully static design * Wide operating voltage range: - 2.5V to 6.0V (PIC16C72) - 2.5V to 5.5V (PIC16CR72) * High Sink/Source Current 25/25 mA * Commercial, Industrial and Extended temperature ranges * Low-power consumption: - < 2 mA @ 5V, 4 MHz - 15 A typical @ 3V, 32 kHz - < 1 A typical standby current
PIC16C72 PIC16CR72
Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Capture, Compare, PWM (CCP) module - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit * 8-bit 5-channel analog-to-digital converter * Synchronous Serial Port (SSP) with SPITM and I2CTM * Brown-out detection circuitry for Brown-out Reset (BOR)
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 1
PIC16C72 Series
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 3 2.0 Memory Organization ................................................................................................................................................................... 5 3.0 I/O Ports ..................................................................................................................................................................................... 19 4.0 Timer0 Module ........................................................................................................................................................................... 25 5.0 Timer1 Module ........................................................................................................................................................................... 27 6.0 Timer2 Module ........................................................................................................................................................................... 31 7.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 33 8.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 39 9.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 53 10.0 Special Features of the CPU...................................................................................................................................................... 59 11.0 Instruction Set Summary ............................................................................................................................................................ 73 12.0 Development Support................................................................................................................................................................. 75 13.0 Electrical Characteristics - PIC16C72 Series ............................................................................................................................. 77 14.0 DC and AC Characteristics Graphs and Tables - PIC16C72 ..................................................................................................... 97 15.0 DC and AC Characteristics Graphs and Tables - PIC16CR72 ................................................................................................ 107 16.0 Packaging Information.............................................................................................................................................................. 109 Appendix A: What's New in this Data Sheet .................................................................................................................................. 115 Appendix B: What's Changed in this Data Sheet........................................................................................................................... 115 Appendix C: Device Differences..................................................................................................................................................... 115 Index .................................................................................................................................................................................................. 117 On-Line Support................................................................................................................................................................................. 121 Reader Response .............................................................................................................................................................................. 122 PIC16C72 Series Product Identification System................................................................................................................................ 125 Sales and Support.............................................................................................................................................................................. 125
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
Key Reference Manual Features Operating Frequency Resets Program Memory - (14-bit words) Data Memory - RAM (8-bit bytes) Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications 8-Bit A/D Converter Instruction Set (No. of Instructions)
PIC16C72 DC - 20MHz POR, PWRT, OST, BOR 2K (EPROM) 128 8 PortA, PortB, PortC Timer0, Timer1, Timer2 1 Basic SSP 5 channels 35
PIC16CR72 DC - 20MHz POR, PWRT, OST, BOR 2K (ROM) 128 8 PortA, PortB, PortC Timer0, Timer1, Timer2 1 SSP 5 channels 35
DS39016A-page 2
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
1.0 DEVICE OVERVIEW
This document contains device-specific information for the operation of the PIC16C72 device. Additional information may be found in the PICmicroTM Mid-Range MCU Reference Manual (DS33023) which may be downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16C72 belongs to the Mid-Range family of the PICmicro devices. A block diagram of the device is shown in Figure 1-1. The program memory contains 2K words which translate to 2048 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 128 bytes. There are also 22 I/O pins that are user-configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: * * * * * * * External interrupt Change on PORTB interrupt Timer0 clock input Timer1 clock/oscillator Capture/Compare/PWM A/D converter SPI/I2C
Table 1-1 details the pinout of the device with descriptions and details for each pin.
FIGURE 1-1:
PIC16C72/CR72 BLOCK DIAGRAM
13 EPROM/ ROM Program Memory 2K x 14 Program Counter Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 PORTB
8 Level Stack (13-bit)
RAM File Registers 128 x 8 RAM Addr(1) 9
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3 PORTC
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7
W reg
MCLR
VDD, VSS
Timer0
Timer1
Timer2
A/D
Synchronous Serial Port
CCP1
Note 1:
Higher order bits are from the STATUS register.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 3
PIC16C72 Series
TABLE 1-1
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16C72/CR72 PINOUT DESCRIPTION
Pin# 9 10 I/O/P Type I O Buffer Type Description
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0. RA1 can also be analog input1. RA2 can also be analog input2. RA3 can also be analog input3 or analog reference voltage RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0 can also be the external interrupt pin.
MCLR/VPP
1
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
2 3 4 5 6 7
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 VSS VDD Legend: I = input
21 22 23 24 25 26 27 28 11 12 13 14 15 16 17 18 8, 19 20
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) ST ST ST ST ST ST ST ST -- --
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input. RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode).
Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS39016A-page 4
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
2.0 MEMORY ORGANIZATION
FIGURE 2-1:
There are two memory blocks in PIC16C72 Series devices. These are the program memory and the data memory. Each block has its own bus, so that access to both blocks can occur during the same oscillator cycle. The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the "core" are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. Additional information on device memory may be found in the PICmicroTM Mid-Range Reference Manual, DS33023.
PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
Stack Level 8 Reset Vector
0000h
2.1
Program Memory Organization
User Memory Space Interrupt Vector 0004h 0005h
PIC16C72 Series devices have a 13-bit program counter capable of addressing a 2K x 14 program memory space. The address range for this program memory is 0000h - 07FFh. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.
On-chip Program Memory 07FFh 0800h
1FFFh
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 5
PIC16C72 Series
2.2 Data Memory Organization FIGURE 2-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC
REGISTER FILE MAP
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1* = 00 = 01 = 10 = 11 * RP0 (STATUS<6:5>)
Bank0 Bank1 Bank2 (not implemented) Bank3 (not implemented)
Maintain this bit clear to ensure upward compatibility with future products.
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some "high use" special function registers from one bank may be mirrored in another bank for code reduction and quicker access (ex; the STATUS register is in Bank 0 and Bank 1). 2.2.1 GENERAL PURPOSE REGISTER FILE
PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON
PCLATH INTCON PIE1 PCON
The register file can be accessed either directly or indirectly through the File Select Register FSR (Section 2.5).
PR2 SSPADD SSPSTAT
ADRES ADCON0 General Purpose Register
ADCON1 General Purpose Register
BFh C0h
7Fh
FFh Bank 0 Bank 1
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
DS39016A-page 6
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. The special function registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 2-1
Address Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (3)
Bank 0 00h(1) 01h 02h(1) 03h(1) 04h(1) 05h 06h 07h 08h 09h 0Ah(1,2) 0Bh(1) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h-1Dh 1Eh 1Fh INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON -- ADRES ADCON0 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 TO PD Z DC C 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --0x 0000 --0u 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- -- -- PEIE ADIF -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE SSPIF T0IF CCP1IF INTF TMR2IF RBIF TMR1IF -- --
Indirect data memory address pointer -- -- PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read Unimplemented Unimplemented -- GIE --
---0 0000 ---0 0000 0000 000x 0000 000u -0-- 0000 -0-- 0000 -- --
Unimplemented Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --uu uuuu 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu
Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) -- Unimplemented A/D Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON -- CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
--00 0000 --00 0000 -- --
xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear. 5: SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 7
PIC16C72 Series
TABLE 2-1
Address Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (3)
Bank 1 80h(1) 81h 82h(1) 83h(1) 84h 85h 86h 87h 88h 89h 8Ah(1,2) 8Bh(1) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh PR2 SSPADD SSPSTAT -- -- -- -- -- -- -- -- -- -- ADCON1
(1)
INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC -- -- PCLATH INTCON PIE1 -- PCON -- -- --
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 TO PD Z DC C
0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 -- -- -- --
Indirect data memory address pointer -- -- PORTA Data Direction Register
PORTB Data Direction Register PORTC Data Direction Register Unimplemented Unimplemented -- GIE -- -- PEIE ADIE -- T0IE -- Write Buffer for the upper 5 bits of the PC INTE -- RBIE SSPIE T0IF CCP1IE INTF TMR2IE RBIF TMR1IE
---0 0000 ---0 0000 0000 000x 0000 000u -0-- 0000 -0-- 0000 -- --
Unimplemented -- Unimplemented Unimplemented Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP(5) CKE(5) D/A P S R/W UA BF -- -- -- -- -- POR BOR
---- --qq ---- --uu -- -- -- -- -- --
1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ---- -000
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0
---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear. 5: SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
DS39016A-page 8
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
2.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 2-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." Note 1: These devices do not use bits IRP and RP1 (STATUS<7:6>). Maintain these bits clear to ensure upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 2-3:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. For devices with only Bank0 and Bank1, the IRP bit is reserved. Always maintain this bit clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 9
PIC16C72 Series
2.2.2.2 OPTION_REG REGISTER Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 2-4:
R/W-1 RBPU bit7
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS39016A-page 10
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
2.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
FIGURE 2-5:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
R/W-0 PEIE
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 11
PIC16C72 Series
2.2.2.4 PIE1 REGISTER Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. This register contains the individual enable bits for the peripheral interrupts.
FIGURE 2-6:
U-0 -- bit7
PIE1 REGISTER (ADDRESS 8Ch)
U-0 -- U-0 -- R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit0
R/W-0 ADIE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as '0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 5-4: Unimplemented: Read as '0' bit 3:
bit 2:
bit 1:
bit 0:
DS39016A-page 12
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
2.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the Peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 2-7:
U-0 -- bit7
PIR1 REGISTER (ADDRESS 0Ch)
U-0 -- U-0 -- R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit0
R/W-0 ADIF
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as '0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow
bit 5-4: Unimplemented: Read as '0' bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 13
PIC16C72 Series
2.2.2.6 PCON REGISTER Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word).
FIGURE 2-8:
U-0 -- bit7
PCON REGISTER (ADDRESS 8Eh)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-q BOR bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 0:
DS39016A-page 14
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
2.3 PCL and PCLATH
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. Figure 2-9 shows the four situations for the loading of the PC. Example 1 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). Example 2 shows how the PC is loaded during a GOTO instruction (PCLATH<4:3> PCH). Example 3 shows how the PC is loaded during a CALL instruction (PCLATH<4:3> PCH), with the PC loaded (PUSHed) onto the Top of Stack. Finally, example 4 shows how the PC is loaded during one of the return instructions where the PC is loaded (POPed) from the Top of Stack.
FIGURE 2-9:
LOADING OF PC IN DIFFERENT SITUATIONS
STACK (13-bits x 8) Top of STACK 0
Situation 1 - Instruction with PCL as destination
PCH 12 PC 5 PCLATH<4:0> 8 ALU result PCLATH 8 7 PCL
Situation 2 - GOTO Instruction
PCH 12 PC 2 PCLATH<4:3> 11 11 10 8 7 PCL 0
STACK (13-bits x 8) Top of STACK
Opcode <10:0>
PCLATH
Situation 3 - CALL Instruction
13 PCH 12 PC 2 PCLATH<4:3> 11 11 10 8 7 PCL 0
STACK (13-bits x 8) Top of STACK
Opcode <10:0>
PCLATH
Situation 4 - RETURN, RETFIE, or RETLW Instruction
13 PCH 12 PC 11 11 10 8 7 PCL 0
STACK (13-bits x 8) Top of STACK
Opcode <10:0>
PCLATH
Note: PCLATH is not updated with the contents of PCH.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 15
PIC16C72 Series
2.3.1 STACK
2.4
Program Memory Paging
The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Midrange devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). An example of the overwriting of the stack is shown in Figure 2-10.
The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack). Note: PIC16C72 Series devices ignore paging bit PCLATH<4>. The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products.
FIGURE 2-10: STACK MODIFICATION
STACK Push1 Push9 Push2 Push10 Push3 Push4 Push5 Push6 Push7 Push8 Top of STACK
DS39016A-page 16
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
2.5 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
EXAMPLE 2-2:
HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
EXAMPLE 2-1:
* * * *
INDIRECT ADDRESSING
Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 06) * A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).
NEXT
movlw movwf clrf incf btfss goto :
CONTINUE
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-11. However, IRP is not used in the PIC16C72 Series.
FIGURE 2-11: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0 6 from opcode 0 IRP
Indirect Addressing
7 FSR register 0
(2)
bank select location select 00 00h 01 80h 10 100h 11 180h
(2)
bank select location select
Data Memory(1)
not used (3) (3)
7Fh
FFh
17Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: For register file map detail see Figure 2-2. 2: Maintain RP1 and IRP as clear for upward compatibility with future products. 3: Not implemented.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 17
PIC16C72 Series
NOTES:
DS39016A-page 18
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
3.0 I/O PORTS
FIGURE 3-1:
Data bus WR Port
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range MCU Reference Manual, DS33023.
BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
Q VDD
D
CK
Q
P
Data Latch
3.1
PORTA and the TRISA Register
WR TRIS
D
Q
N
I/O pin(1)
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin. Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
CK
Q
TRIS Latch
VSS Analog input mode
RD TRIS Q D
TTL input buffer
EN RD PORT
To A/D Converter Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 3-2:
Data bus WR PORT
BLOCK DIAGRAM OF RA4/ T0CKI PIN
D Q Q
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
CK
N Data Latch
D Q Q
I/O pin(1)
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6> are always read as '0'.
VSS Schmitt Trigger input buffer
STATUS, RP0 PORTA
WR TRIS
CK
TRIS Latch
BSF MOVLW
STATUS, RP0 0xCF
RD TRIS
Q D EN EN
MOVWF
TRISA
RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 19
PIC16C72 Series
TABLE 3-1
Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 Buffer TTL TTL TTL TTL ST Function
Input/output or analog input Input/output or analog input Input/output or analog input Input/output or analog input or VREF Input/output or external clock input for Timer0 Output is open drain type RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2
Address Name 05h 85h 9Fh PORTA TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 Bit 6 -- -- -- -- -- -- Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on: POR, BOR --0x 0000 --11 1111 PCFG2 PCFG1 PCFG0 ---- -000 Value on all other resets --0u 0000 --11 1111 ---- -000
PORTA Data Direction Register -- -- --
ADCON1
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS39016A-page 20
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
STATUS, RP0 PORTB
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-4:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
FIGURE 3-3:
RBPU(2)
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
RBPU(2)
Data bus WR Port
Data bus WR Port
WR TRIS TTL Input Buffer
CK
TTL Input Buffer
ST Buffer
WR TRIS
CK
RD TRIS Q RD TRIS Q RD Port D EN From other RB7:RB4 pins RB0/INT Schmitt Trigger Buffer RD Port RB7:RB6 in serial programming mode Set RBIF RD Port
Latch D EN Q1
Q
D RD Port EN Q3
Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>).
Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>).
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 21
PIC16C72 Series
TABLE 3-3
Name RB0/INT
PORTB FUNCTIONS
Bit# bit0 Buffer TTL/ST(1) Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4
Address 06h, 106h 86h, 186h 81h, 181h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name PORTB TRISB OPTION Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on: POR, BOR xxxx xxxx 1111 1111 PSA PS2 PS1 PS0 1111 1111 Value on all other resets uuuu uuuu 1111 1111 1111 1111
PORTB Data Direction Register RBPU INTEDG T0CS T0SE
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS39016A-page 22
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
3.3 PORTC and the TRISC Register FIGURE 3-5:
PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin. PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORT/PERIPHERAL Select(2) Peripheral Data Out Data bus WR PORT
D CK Q
0 1
Q
VDD P
Data Latch WR TRIS
D CK Q Q
I/O pin(1) N VSS
TRIS Latch Schmitt Trigger
Q D EN
RD TRIS Peripheral OE(3) RD PORT Peripheral input
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTC
; ; ; ; ; ; ; ; ; ; ; Select Bank 0 Initialize PORTC by clearing output data latches Select Bank 1 Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs
STATUS, RP0 PORTC
BSF MOVLW
STATUS, RP0 0xCF
Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active.
MOVWF
TRISC
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 23
PIC16C72 Series
TABLE 3-5
Name RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7
PORTC FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input Input/output port pin or Timer1 oscillator input Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output Input/output port pin Input/output port pin
Legend: ST = Schmitt Trigger input
TABLE 3-6
Address Name 07h 87h PORTC TRISC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on: POR, BOR xxxx xxxx 1111 1111 Value on all other resets uuuu uuuu 1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged.
DS39016A-page 24
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable Internal or external clock select Edge select for external clock 8-bit software programmable prescaler Interrupt on overflow from FFh to 00h Additional information on external clock requirements is available in the PICmicroTM Mid-Range MCU Reference Manual, DS33023.
4.2
Prescaler
Figure 4-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Reference Manual, DS33023.
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
4.1
Timer0 Operation
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in below. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization.
FIGURE 4-1:
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler T0SE 3 PS2, PS1, PS0 T0CS PSA Set interrupt flag bit T0IF on overflow PSout Sync with Internal clocks (2 cycle delay) TMR0 PSout 8
RA4/T0CKI pin
0
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 25
PIC16C72 Series
4.2.1 SWITCHING PRESCALER ASSIGNMENT
4.3
Timer0 Interrupt
The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicroTM Mid-Range MCU Reference Manual, DS3023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 4-2:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1
Address 01h,101h
REGISTERS ASSOCIATED WITH TIMER0
Name TMR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR xxxx xxxx INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 --11 1111 Value on all other resets uuuu uuuu 0000 000u 1111 1111 --11 1111
Timer0 module's register GIE PEIE T0IE T0CS
0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h 85h OPTION_REG TRISA
RBPU INTEDG -- --
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS39016A-page 26
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
5.0 TIMER1 MODULE
5.1 Timer1 Operation
The Timer1 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L) * Readable and writable (Both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * Reset from CCP module trigger Timer1 has a control register, shown in Figure 5-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Figure 5-2 is a simplified block diagram of the Timer1 module. Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Reference Manual, DS33023. Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer1 also has an internal "reset input". This reset can be generated by the CCP module (Section 7.0).
FIGURE 5-1:
U-0 -- bit7
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON bit0
bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1
bit 2:
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 27
PIC16C72 Series
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
Set flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0 1 TMR1ON on/off T1SYNC
Synchronized clock input
T1OSC RC0/T1OSO/T1CKI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input Synchronize det
RC1/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39016A-page 28
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
5.2 Timer1 Oscillator 5.3 Timer1 Interrupt
A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4
Resetting Timer1 using a CCP Trigger Output
TABLE 5-1
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Freq 32 kHz 100 kHz 200 kHz C1 33 pF 15 pF 15 pF C2 33 pF 15 pF 15 pF
If the CCP module is configured in compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
Osc Type LP
These values are for design guidance only.
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.
Crystals Tested: 32.768 kHz Epson C-001R32.768K-A 20 PPM 100 kHz Epson C-2 100.00 KC-P 20 PPM 200 kHz STD XTL 200.000 kHz 20 PPM Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
TABLE 5-2
Address Name 0Bh,8Bh 0Ch 8Ch 0Eh 0Fh 10h
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 GIE
(1) (1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE
(1) (1)
Bit 4 INTE
(1) (1)
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF CCP1IF CCP1IE
Bit 1 INTF TMR2IF TMR2IE
Bit 0 RBIF TMR1IF TMR1IE
Value on: POR, BOR
Value on all other resets
INTCON PIR1 PIE1 TMR1L TMR1H T1CON
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented, read as '0'.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 29
PIC16C72 Series
NOTES:
DS39016A-page 30
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
6.0
* * * * * * *
TIMER2 MODULE
6.2
Timer2 Interrupt
The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (Both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift
The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset.
6.3
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock.
Timer2 has a control register, shown in Figure 6-2. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 6-1 is a simplified block diagram of the Timer2 module. Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Reference Manual, DS33023.
FIGURE 6-1:
Sets flag bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2 output (1) Reset Prescaler 1:1, 1:4, 1:16 2
TMR2 reg Comparator
FOSC/4
Postscaler 1:1 to 1:16 4
EQ
6.1
Timer2 Operation
PR2 reg
Timer2 can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR2 register * a write to the T2CON register * any device reset (Power-on Reset, MCLR reset, Watchdog Timer reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written.
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 31
PIC16C72 Series
FIGURE 6-2:
U-0 -- bit7
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7: bit 6-3:
Unimplemented: Read as '0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
bit 2:
bit 1-0:
TABLE 6-1
Address 0Bh,8Bh 0Ch 8Ch 11h 12h 92h Legend: 2: Name INTCON PIR1 PIE1 TMR2 T2CON PR2
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7 GIE
(1) (1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE
(1) (1)
Bit 4 INTE
(1) (1)
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF CCP1IF CCP1IE
Bit 1 INTF TMR2IF TMR2IE
Bit 0 RBIF TMR1IF TMR1IE
Value on: POR, BOR
Value on all other resets
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111
Timer2 Period Register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. These bits are unimplemented, read as '0'.
DS39016A-page 32
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
7.0 CAPTURE/COMPARE/PWM (CCP) MODULE
Additional information on the CCP module is available in the PICmicroTM Mid-Range MCU Reference Manual, DS33023.
The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes. Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable.
TABLE 7-1
CCP MODE - TIMER RESOURCE
Timer Resource Timer1 Timer1 Timer2
CCP Mode Capture Compare PWM
FIGURE 7-1:
U-0 -- bit7 U-0 --
CCP1CON REGISTER (ADDRESS 17h)
R/W-0 R/W-0 R/W-0 CCP1X CCP1Y CCP1M3 R/W-0 CCP1M2 R/W-0 R/W-0 CCP1M1 CCP1M0 bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7-6: Unimplemented: Read as '0' bit 5-4: CCP1X:CCP1Y: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 33
PIC16C72 Series
7.1 Capture Mode
7.1.4 CCP PRESCALER In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. 7.1.1 CCP PIN CONFIGURATION
EXAMPLE 7-1:
CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition.
CCP1CON NEW_CAPT_PS
MOVWF
CCP1CON
FIGURE 7-2:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set flag bit CCP1IF (PIR1<2>)
Prescaler / 1, 4, 16 RC2/CCP1 Pin and edge detect
CCPR1H Capture Enable TMR1H CCP1CON<3:0> Q's
CCPR1L
TMR1L
7.1.2
TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. 7.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode.
DS39016A-page 34
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
7.2 Compare Mode
7.2.1 CCP PIN CONFIGURATION In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: * driven High * driven Low * remains Unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch. TIMER1 MODE SELECTION
7.2.2
FIGURE 7-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 7.2.3 SOFTWARE INTERRUPT MODE
Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion Special Event Trigger Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S Output Logic match RC2/CCP1 R Pin TRISC<2> Output Enable CCP1CON<3:0> Mode Select Comparator TMR1H TMR1L
When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). 7.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special trigger output of CCP1 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
TABLE 7-2
Address
0Bh,8Bh 0Ch 8Ch 87h 0Eh 0Fh 10h 15h 16h 17h
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Bit 7
GIE
(1) (1)
Name
INTCON PIR1 PIE1 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON
Bit 6
PEIE ADIF ADIE
Bit 5
T0IE
(1) (1)
Bit 4
INTE
(1) (1)
Bit 3
RBIE SSPIF SSPIE
Bit 2
T0IF CCP1IF CCP1IE
Bit 1
INTF TMR2IF TMR2IE
Bit 0
RBIF
Value on: POR, BOR
Value on all other resets
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
PORTC Data Direction Register Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- CCP1X CCP1Y
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: These bits/registers are unimplemented, read as '0'.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 35
PIC16C72 Series
7.3 PWM Mode
7.3.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] 4 TOSC (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 6.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE
Figure 7-4 shows a simplified block diagram of the CCP module in PWM mode. For a step by step procedure on how to set up the CCP module for PWM operation, see Section 7.3.3.
FIGURE 7-4:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty cycle registers CCPR1L
7.3.2
CCPR1H (Slave)
Comparator
R
Q RC2/CCP1
TMR2
(Note 1) S TRISC<2> Clear Timer, CCP1 pin and latch D.C.
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) Tosc (TMR2 prescale value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency: FOSC log( FPWM log(2)
Comparator
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 7-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 7-5:
PWM OUTPUT
Period
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 Note:
=
)
bits
If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared.
DS39016A-page 36
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
For an example PWM period and duty cycle calculation, see the PICmicroTM Mid-Range MCU Reference Manual (DS33023). 7.3.3 SET-UP FOR PWM OPERATION 3. 4. 5. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits.
TABLE 7-3
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 0xFF 10 4 0xFF 10 1 0xFF 10 1 0x3F 8 1 0x1F 7 1 0x17 5.5
Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 7-4
Address 0Bh,8Bh 0Ch 8Ch Name INTCON PIR1 PIE1
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 GIE
(1) (1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE
(1) (1)
Bit 4 INTE
(1) (1)
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF CCP1IF CCP1IE
Bit 1 INTF TMR2IF TMR2IE
Bit 0 RBIF
Value on: POR, BOR
Value on all other resets
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000
87h
11h 92h 12h 15h 16h 17h Legend: Note 1:
TRISC
TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON
PORTC Data Direction Register
Timer2 module's register Timer2 module's period register -- TOUTPS TOUTPS TOUTPS TOUTPS 3 2 1 0 TMR2O N
1111 1111 1111 1111
0000 0000 0000 0000 1111 1111 1111 1111 T2CKPS T2CKPS -000 0000 -000 0000 1 0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- CCP1X CCP1Y
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. These bits/registers are unimplemented, read as '0'.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 37
PIC16C72 Series
NOTES:
DS39016A-page 38
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
8.0
8.1
SYNCHRONOUS SERIAL PORT (SSP) MODULE
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) The SSP module in I2C mode works the same in all PIC16C72 series devices that have an SSP module. However the SSP Module in SPI mode has differences between the PIC16C72 and the PIC16CR72 device. The register definitions and operational description of SPI mode has been split into two sections because of the differences between the PIC16C72 and the PIC16CR72 device. The default reset values of both the SPI modules is the same regardless of the device: 8.2 8.3 8.4 SPI Mode for PIC16C72 .................................. 40 SPI Mode for PIC16CR72 ............................... 43 SSP I2C Operation .......................................... 47
For an I2C Overview, refer to the PICmicroTM MidRange MCU Reference Manual (DS33023). Also, refer to Application Note AN578, "Use of the SSP Module in the I 2C Multi-Master Environment."
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 39
PIC16C72 Series
8.2 SPI Mode for PIC16C72
This section contains register definitions and operational characteristics of the SPI module on the PIC16C72 device only. Additional information on SPI operation may be found in the PICmicroTM Mid-Range MCU Reference Manual, DS33023.
FIGURE 8-1:
U-0 -- bit7 U-0 --
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) (PIC16C72)
R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7-6: Unimplemented: Read as '0' bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
DS39016A-page 40
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
FIGURE 8-2:
R/W-0 WCOL bit7
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) (PIC16C72)
R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit0
R/W-0 SSPOV
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Detect bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR register is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow
bit 6:
bit 5:
SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge. 0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge. In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master operation, clock = Fosc/4 0001 = SPI master operation, clock = Fosc/16 0010 = SPI master operation, clock = Fosc/64 0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master operation (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 41
PIC16C72 Series
8.2.1 OPERATION OF SSP MODULE IN SPI MODE - PIC16C72 * SCK (Slave mode) must have TRISC<3> set * SS must have TRISA<5> set (if implemented)
A block diagram of the SSP Module in SPI Mode is shown in Figure 8-3. The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) RC5/SDO RC4/SDI/SDA RC3/SCK/SCL
FIGURE 8-3:
SSP BLOCK DIAGRAM (SPI MODE)
Internal data bus Read SSPBUF reg Write
Additionally a fourth pin may be used when in a slave mode of operation: * Slave Select (SS) RA5/SS/AN4
RC4/SDI/SDA RC5/SDO bit0 SSPSR reg shift clock
When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>). These control bits allow the following to be specified: * Master Operation (SCK is the clock output) * Slave Mode (SCK is the clock input) * Clock Polarity (Output/Input data on the Rising/ Falling edge of SCK) * Clock Rate (master operation only) * Slave Select Mode (Slave mode only) To enable the serial port, SSP enable bit SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear enable bit SSPEN, re-initialize SSPCON register, and then set enable bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRIS register) appropriately programmed. That is: * SDI must have TRISC<4> set * SDO must have TRISC<5> cleared * SCK (master operation) must have TRISC<3> cleared
SS Control Enable RA5/SS/AN4 Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TRISC<3>
TMR2 output 2 Prescaler TCY 4, 16, 64
TABLE 8-1
Address 0Bh,8Bh 0Ch 8Ch 87h 13h 14h 85h 94h Name
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7 GIE
(1) (1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE
(1) (1)
Bit 4 INTE
(1) (1)
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF
Bit 1 INTF
Bit 0 RBIF
Value on: POR, BOR
Value on all other resets
INTCON PIR1 PIE1 TRISC SSPBUF SSPCON TRISA SSPSTAT
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM1 SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 UA BF --00 0000 --00 0000
PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register WCOL -- -- SSPOV SSPEN -- -- CKP SSPM3 SSPM2
PORTA Data Direction Register D/A P S R/W
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: These bits are unimplemented, read as '0'.
DS39016A-page 42
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
8.3 SPI Mode for PIC16CR72
This section contains register definitions and operational characteristics of the SPI module on the PIC16CR72 device only. Additional information on SPI operation may be found in the PICmicroTM Mid-Range MCU Reference Manual, DS33023.
FIGURE 8-4:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) (PIC16CR72)
R/W-0 R/W-0 SMP bit7 CKE
R-0 D/A
R-0 P
R-0 S
R-0 R/W
R-0 UA
R-0 BF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
SMP: SPI data input sample phase SPI Master Operation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode CKE: SPI Clock Edge Select CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 43
PIC16C72 Series
FIGURE 8-5: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) (PIC16CR72)
R/W-0 WCOL bit7
R/W-0 SSPOV
R/W-0 SSPEN
R/W-0 CKP
R/W-0 SSPM3
R/W-0 SSPM2
R/W-0 SSPM1
R/W-0 SSPM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow
bit 6:
bit 5:
SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master operation, clock = FOSC/4 0001 = SPI master operation, clock = FOSC/16 0010 = SPI master operation, clock = FOSC/64 0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master operation (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
DS39016A-page 44
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
8.3.1 OPERATION OF SSP MODULE IN SPI MODE - PIC16CR72
FIGURE 8-6:
SSP BLOCK DIAGRAM (SPI MODE)(PIC16CR72)
Internal data bus Read SSPBUF reg Write
A block diagram of the SSP Module in SPI Mode is shown in Figure 8-6. The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) RC5/SDO RC4/SDI/SDA RC3/SCK/SCL
SSPSR reg RC4/SDI/SDA RC5/SDO bit0 shift clock
Additionally a fourth pin may be used when in a slave mode of operation: * Slave Select (SS) RA5/SS/AN4 When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: * * * * Master Operation (SCK is the clock output) Slave Mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock Edge (Output data on rising/falling edge of SCK) * Clock Rate (master operation only) * Slave Select Mode (Slave mode only)
SS Control Enable RA5/SS/AN4 Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TRISC<3>
TMR2 output 2 Prescaler TCY 4, 16, 64
To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: * SDI must have TRISC<4> set * SDO must have TRISC<5> cleared * SCK (master operation) must have TRISC<3> cleared * SCK (Slave mode) must have TRISC<3> set * SS must have TRISA<5> set Note: When the SPI is in Slave Mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set to VDD. If the SPI is used in Slave Mode with CKE = '1', then the SS pin control must be enabled.
Note:
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 45
PIC16C72 Series
TABLE 8-2
Address 0Bh,8Bh 0Ch 8Ch 87h 13h 14h 85h 94h Name INTCON PIR1 PIE1 TRISC SSPBUF
REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16CR72)
Bit 7 GIE
(1) (1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE
(1) (1)
Bit 4 INTE
(1) (1)
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF
Bit 1 INTF
Bit 0 RBIF
Value on: POR, BOR
Value on all other resets
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM1 SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 UA BF 0000 0000 0000 0000
PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register SSPOV SSPEN -- CKE CKP SSPM3 SSPM2
SSPCON WCOL TRISA SSPSTAT -- SMP
PORTA Data Direction Register D/A P S R/W
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Always maintain these bits clear.
DS39016A-page 46
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
8.4 SSP I 2C Operation
The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>). The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address), with start and stop bit interrupts enabled * I 2C Slave mode (10-bit address), with start and stop bit interrupts enabled * I 2C Firmware controlled master operation, slave is idle Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. Additional information on SSP I2C operation may be found in the PICmicroTM Mid-Range MCU Reference Manual, DS33023. 8.4.1 SLAVE MODE
FIGURE 8-7:
SSP BLOCK DIAGRAM (I2C MODE)
Internal data bus Read SSPBUF reg shift clock SSPSR reg Write
RC3/SCK/SCL
In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register.
Addr Match
RC4/ SDI/ SDA
MSb
LSb
Match detect
There are certain conditions that will cause the SSP module not to give this ACK pulse. These are if either (or both): a) The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received.
SSPADD reg Start and Stop bit detect Set, Reset S, P bits (SSPSTAT reg)
b)
The SSP module has five registers for I2C operation. These are the: SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible * SSP Address Register (SSPADD) * * * *
In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 8-3 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification as well as the requirement of the SSP module is shown in timing parameter #100 and parameter #101.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 47
PIC16C72 Series
8.4.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth SCL pulse. `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. 2. Receive first (high) byte of Address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address, if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated START condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
3. 4. 5.
6. 7. 8. 9.
In 10-bit address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte would equal
TABLE 8-3
DATA TRANSFER RECEIVED BYTE ACTIONS
Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes
Status Bits as Data Transfer is Received BF 0 1 1 0 SSPOV 0 0 1 1 SSPSR SSPBUF Yes No No No Generate ACK Pulse Yes No No No
DS39016A-page 48
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
8.4.1.2 RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte.
FIGURE 8-8:
I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
Receiving Address Receiving Data R/W=0 Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL
SSPIF (PIR1<3>)
Cleared in software
Bus Master terminates transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 49
PIC16C72 Series
8.4.1.3 TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 8-9). An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 8-9:
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK
SDA
A7
A6
A5
A4
A3
A2
SCL
S
1 2 Data in sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>) BF (SSPSTAT<0>)
cleared in software
SSPBUF is written in software CKP (SSPCON<4>)
From SSP interrupt service routine
Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set)
DS39016A-page 50
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
8.4.2 MASTER OPERATION 8.4.3 MULTI-MASTER OPERATION Master operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle and both the S and P bits are clear. In master operation, the SCL and SDA lines are manipulated in firmware by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit. The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): * START condition * STOP condition * Data transfer byte transmitted/received Master operation can be done with either the slave mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt. For more information on master operation, see AN554 - Software Implementation of I2C Bus Master. In multi-master operation, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are: * Address Transfer * Data Transfer When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. For more information on master operation, see AN578 - Use of the SSP Module in the of I2C Multi-Master Environment.
TABLE 8-4
Address Name
REGISTERS ASSOCIATED WITH I2C OPERATION
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 000x Value on all other resets 0000 000u
0Bh, 8Bh, 10Bh,18Bh 0Ch 8Ch 13h 93h 14h 94h 87h
INTCON PIR1 PIE1
GIE
(1) (1)
PEIE ADIF ADIE
T0IE
(1) (1)
INTE
(1) (1)
RBIE
T0IF
INTF
RBIF
SSPIF CCP1IF TMR2IF TMR1IF SSPIE CCP1IE TMR2IE TMR1IE
0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 1111 1111
0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register SSPADD Synchronous Serial Port SSPCON SSPSTAT TRISC WCOL SMP(2) (I2C mode) Address Register CKP P SSPM3 SSPM2 SSPM1 SSPM0 S R/W UA BF
SSPOV SSPEN CKE(2) D/A
PORTC Data Direction register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: These bits are unimplemented, read as '0'. 2: The SMP and CKE bits are implemented on the PIC16CR72 only. On the PIC16C72, these two bits are unimplemented, read as '0'.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 51
PIC16C72 Series
NOTES:
DS39016A-page 52
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
9.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
Additional information on the A/D module is available in the PICmicroTM Mid-Range MCU Reference Manual, DS33023. The A/D module has three registers. These registers are: * A/D Result Register (ADRES) * A/D Control Register 0 (ADCON0) * A/D Control Register 1 (ADCON1) A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The ADCON0 register, shown in Figure 9-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 9-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as digital I/O.
The analog-to-digital (A/D) converter module has five inputs for the PIC16C72/R72. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD) or the voltage level on the RA3/AN3/VREF pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator.
FIGURE 9-1:
ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit0
R/W-0 R/W-0 ADCS1 ADCS0 bit7
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an internal RC oscillator) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: bit 0: Unimplemented: Read as '0' ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 53
PIC16C72 Series
FIGURE 9-2:
U-0 -- bit7
ADCON1 REGISTER (ADDRESS 9Fh)
U-0 -- U-0 -- U-0 -- R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0
U-0 --
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x A = Analog input D = Digital I/O RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D VREF VDD RA3 VDD RA3 VDD RA3 GND
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 9-3. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 9.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins / voltage reference / and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts.
3. 4. 5.
FIGURE 9-3:
A/D BLOCK DIAGRAM
CHS2:CHS0
100 VAIN (Input voltage) 011 010 A/D Converter 001
RA5/AN4 RA3/AN3/VREF RA2/AN2 RA1/AN1
VDD VREF (Reference voltage) PCFG2:PCFG0 000 or 010 or 100 001 or 011 or 101
000 RA0/AN0
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 55
PIC16C72 Series
9.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, TACQ, see the PICmicroTM Mid-Range MCU Reference Manual, DS33023. This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy.
FIGURE 9-4:
ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS CHOLD = DAC capacitance = 51.2 pF VSS Legend CPIN = input capacitance = threshold voltage VT I leakage = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
Rs
ANx
VA
CPIN 5 pF
VT = 0.6V
I leakage 500 nA
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch ( k )
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
9.2 Selecting the A/D Conversion Clock 9.3 Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: * * * * 2TOSC 8TOSC 32TOSC Internal RC oscillator The ADCON1, TRISA, and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins), may cause the input buffer to consume current that is out of the devices specification.
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 9-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 9-1
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency 20 MHz 100 ns(2) ns(2)
(1,4)
AD Clock Source (TAD) Operation 2TOSC 8TOSC 32TOSC RC(5) Legend: Note 1: 2: 3: 4: ADCS1:ADCS0 00 01 10 11
5 MHz 400 1.6 s ns(2)
1.25 MHz 1.6 s 6.4 s 25.6 s(3) s(1,4)
333.33 kHz 6 s 24 s(3) 96 s(3)
400 1.6 s
6.4 s s(1,4)
2-6 2-6 2 - 6 s(1) 2 - 6 s Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section.
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Preliminary
DS39016A-page 57
PIC16C72 Series
9.4
Note:
A/D Conversions
The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
9.5
Use of the CCP Trigger
An A/D conversion can be started by the "special event trigger" of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter.
TABLE 9-2
Address 0Bh,8Bh 0Ch 8Ch 1Eh 1Fh 9Fh 05h Name
REGISTERS/BITS ASSOCIATED WITH A/D
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE SSPIF SSPIE Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF Bit 0 RBIF Value on: POR, BOR 0000 000x Value on all other Resets 0000 000u -0-- 0000 -0-- 0000 uuuu uuuu 0000 00-0 ---- -000 --0u 0000 --11 1111
INTCON PIR1 PIE1 ADRES
TMR2IF TMR1IF -0-- 0000 TMR2IE TMR1IE -0-- 0000 xxxx xxxx
A/D Result Register CHS0 -- RA3 GO/DONE PCFG2 RA2 -- PCFG1 RA1 ADON PCFG0 RA0
ADCON0 ADCS1 ADCS0 CHS2 CHS1 ADCON1 PORTA -- -- -- -- -- RA5 -- RA4
0000 00-0 ---- -000 --0x 0000 --11 1111
85h TRISA -- -- PORTA Data Direction Register Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
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(c) 1998 Microchip Technology Inc.
PIC16C72 Series
10.0 SPECIAL FEATURES OF THE CPU
ble. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. Additional information on special features is available in the PICmicroTM Mid-Range MCU Family Reference Manual, DS33023.
The PIC16C72 series has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * Oscillator selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-Circuit Serial ProgrammingTM The PIC16CXXX family has a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is sta-
10.1
Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming.
FIGURE 10-1: CONFIGURATION WORD FOR PIC16C72/R72
CP1 bit13 CP0 CP1 CP0 CP1 CP0 -- BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 bit0
Register:CONFIG Address2007h
bit 13-8 5-4:
CP1:CP0: Code Protection bits (2) 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected Unimplemented: Read as '1' BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 7: bit 6:
bit 3:
bit 2:
bit 1-0:
Note 1:
Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
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Preliminary
DS39016A-page 59
PIC16C72 Series
10.2
10.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 10-1
Ranges Tested: Mode XT
CERAMIC RESONATORS
The PIC16CXXX family can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR/CERAMIC RESONATORS
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz
OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
HS
These values are for design guidance only. See notes at bottom of page.
10.2.2
Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5%
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 10-2). The PIC16CXXX family oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure 10-3).
All resonators used did not have built-in capacitors.
TABLE 10-2
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
Osc Type LP XT
FIGURE 10-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
C1(1) OSC1 To internal logic SLEEP PIC16CXXX
HS
4 MHz 8 MHz 20 MHz
XTAL OSC2 C2(1) Note1: 2: 3: RS(2)
RF(3)
These values are for design guidance only. See notes at bottom of page. Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM
See Table 10-1 and Table 10-2 for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the crystal chosen.
FIGURE 10-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
Clock from ext. system Open OSC1 PIC16CXXX OSC2
Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 10-1). 2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification.
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
10.2.3 RC OSCILLATOR
10.3
Reset
For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 10-4 shows how the R/C combination is connected to the PIC16CXXX family.
The PIC16CXXX family differentiates between various kinds of reset: * * * * * Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (normal operation) Brown-out Reset (BOR)
FIGURE 10-4: RC OSCILLATOR MODE
VDD Rext OSC1 Cext VSS Fosc/4 Recommended values: OSC2/CLKOUT 3 k Rext 100 k Cext > 20pF Internal clock PIC16CXXX
Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR reset during SLEEP, and Brownout Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 10-5. The PIC16C72/CR72 have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low.
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Preliminary
DS39016A-page 61
PIC16C72 Series
FIGURE 10-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset MCLR WDT Module VDD rise detect VDD Brown-out Reset OST/PWRT OST 10-bit Ripple counter OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter R Q Chip_Reset Power-on Reset S SLEEP WDT Time-out Reset
BODEN
Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
10.4 Power-On Reset (POR) 10.5 Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. For a slow rise time, see Figure 10-6. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the startup conditions. The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details.
10.6
Oscillator Start-up Timer (OST)
FIGURE 10-6: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD D R R1 MCLR C PIC16CXXX
The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
10.7
Brown-Out Reset (BOR)
Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for greater than parameter #35, the brown-out situation will reset the chip. A reset may not occur if VDD falls below 4.0V for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will now be invoked and will keep the chip in RESET an additional 72 ms. If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute a 72 ms time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 63
PIC16C72 Series
10.8 Time-out Sequence 10.9
On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 10-7, Figure 10-8, Figure 10-9 and Figure 10-10 depict timeout sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 10-9). This is useful for testing purposes or to synchronize more than one PIC16CXXX family device operating in parallel. Table 10-5 shows the reset conditions for some special function registers, while Table 10-6 shows the reset conditions for all the registers.
Power Control/Status Register (PCON)
The Power Control/Status Register, PCON has up to two bits, depending upon the device. Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent resets to see if bit BOR cleared, indicating a BOR occurred. The BOR bit is a "Don't Care" bit and is not necessarily predictable if the Brown-out Reset circuitry is disabled (by clearing bit BODEN in the Configuration Word). Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.
TABLE 10-3
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 72 ms + 1024TOSC 72 ms PWRTE = 1 1024TOSC -- Brown-out 72 ms + 1024TOSC 72 ms Wake-up from SLEEP 1024TOSC --
Oscillator Configuration XT, HS, LP RC
TABLE 10-4
POR 0 0 0 1 1 1 1 1 BOR x x x 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
TO 1 0 x x 0 0 u 1 PD 1 x 0 x 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 10-5
RESET CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1(1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP
Note 1:
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
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PIC16C72 Series
TABLE 10-6
Register W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRES ADCON0 OPTION TRISA TRISB TRISC PIE1 PCON PR2 SSPADD SSPSTAT ADCON1
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset, Brown-out Reset xxxx xxxx N/A xxxx xxxx 0000h 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx xxxx xxxx ---0 0000 0000 000x -0-- 0000 xxxx xxxx xxxx xxxx --00 0000 0000 0000 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 -0-- 0000 ---- --0u 1111 1111 0000 0000 --00 0000 ---- -000 MCLR Resets WDT Reset uuuu uuuu N/A uuuu uuuu 0000h 000q quuu(3) uuuu uuuu --0u 0000 uuuu uuuu uuuu uuuu ---0 0000 0000 000u -0-- 0000 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 -000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 -0-- 0000 ---- --uu 1111 1111 0000 0000 --00 0000 ---- -000 Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) -u-- uuuu(1) uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uu-u uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu -u-- uuuu ---- --uu 1111 1111 uuuu uuuu --uu uuuu ---- -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 10-5 for reset value for specific condition.
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Preliminary
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FIGURE 10-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
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(c) 1998 Microchip Technology Inc.
PIC16C72 Series
FIGURE 10-10: SLOW RISE TIME (MCLR TIED TO VDD)
5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 0V 1V
(c) 1998 Microchip Technology Inc.
Preliminary
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10.10 Interrupts
The PIC16C72/CR72 has 8 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit 10.10.1 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 10.13 for details on SLEEP mode. 10.10.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 4.0) 10.10.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 3.2)
A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset. The "return from interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts.
FIGURE 10-11: INTERRUPT LOGIC
T0IF T0IE ADIF ADIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE TMR2IF TMR2IE INTF INTE RBIF RBIE PEIE GIE
Wake-up (If in SLEEP mode)
Interrupt to CPU Clear GIE bit
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10.11 Context Saving During Interrupts
The example: a) b) c) d) e) Stores the W register. Stores the STATUS register in bank 0. Executes the ISR code. Restores the STATUS register (and bank select bit). Restores the W register. During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, i.e., W register and STATUS register. This will have to be implemented in software. Example 10-1 stores and restores the W and STATUS registers. The register, W_TEMP, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1).
EXAMPLE 10-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to W_TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :Interrupt Service Routine (ISR) - user defined : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W
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10.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing configuration bit WDTE (Section 10.1). WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition.
. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
FIGURE 10-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 4-2) 0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX WDT Enable Bit PSA To TMR0 (Figure 4-2) 0 MUX 1 PSA PS2:PS0
Note: PSA and PS2:PS0 are bits in the OPTION register.
WDT Time-out
FIGURE 10-13: SUMMARY OF WATCHDOG TIMER REGISTERS
Address 2007h 81h,181h Name Config. bits OPTION Bit 7 (1) RBPU Bit 6 BODEN(1) INTEDG Bit 5 CP1 T0CS Bit 4 CP0 T0SE Bit 3 PWRTE(1) PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 10-1 for operation of these bits.
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10.13 Power-down Mode (SLEEP)
Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 10.13.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 10.13.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change, or some Peripheral Interrupts.
External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. SSP (Start/Stop) bit detect interrupt. SSP transmit or receive in slave mode (SPI/I2C). CCP capture mode interrupt. A/D conversion (when A/D clock source is RC). Special event trigger (Timer1 in asynchronous mode using an external clock).
(c) 1998 Microchip Technology Inc.
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FIGURE 10-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
10.14
Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices.
10.15
ID Locations
Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used. For ROM devices, these values are submitted along with the ROM code.
10.16
In-Circuit Serial ProgrammingTM
PIC16CXXX family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSPTM) Guide, DS30277.
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11.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX family instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXXX family instruction set summary in Table 11-2 lists byteoriented, bit-oriented, and literal and control operations. Table 11-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. Table 11-2 lists the instructions recognized by the MPASM assembler. Figure 11-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16CXXX products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
FIGURE 11-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0 8 7 k (literal) 0 0
TABLE 11-1
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label
0
d
PC TO PD
Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Program Counter Time-out bit Power-down bit
k = 11-bit immediate value
The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s.
A description of each instruction is available in the PICmicroTM Mid-Range MCU Family Reference Manual, DS33023.
(c) 1998 Microchip Technology Inc.
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TABLE 11-2
Mnemonic, Operands
PIC16CXXX INSTRUCTION SET
Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS 14-Bit Opcode LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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12.0
12.1
DEVELOPMENT SUPPORT
Development Tools
The PICmicrTM microcontrollers are supported with a full range of hardware and software development tools: * PICMASTER(R)/PICMASTER CE Real-Time In-Circuit Emulator * ICEPICTM Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLABTM SIM Software Simulator * MPLAB-C17 (C Compiler) * Fuzzy Logic Development System (fuzzyTECH(R)-MP) A description of each development tool is available in the Midrange Reference Manual, DS33023.
12.2
PICDEM-2 Low-Cost PIC16CXX Demonstration Board
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
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NOTES:
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13.0 ELECTRICAL CHARACTERISTICS - PIC16C72 SERIES
Parameter Ambient temperature under bias Storage temperature PIC16C72 -55 to +125C -65C to +150C PIC16CR72 -55 to +125C -65C to +150C Absolute Maximum Ratings
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS Voltage on MCLR with respect to VSS (Note 1) Voltage on RA4 with respect to Vss Total power dissipation (Note 2) Maximum current out of VSS pin Maximum current into VDD pin Input clamp current, IIK (VI < 0 or VI > VDD) Output clamp current, IOK (VO < 0 or VO > VDD) Maximum output current sunk by any I/O pin Maximum output current sourced by any I/O pin Maximum current sunk by PORTA and PORTB (combined) Maximum current sourced by PORTA and PORTB (combined) Maximum current sunk by PORTC Maximum current sourced by PORTC 1. -0.3 to +7.5V -0.3 to +14V -0.3 to +14V 1.0W 300 mA 250 mA 20 mA 20 mA 25 mA 25 mA 200 mA 200 mA 200 mA 200 mA TBD TBD TBD 1.0W 300 mA 250 mA 20 mA 20 mA 25 mA 25 mA 200 mA 200 mA 200 mA 200 mA
2.
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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TABLE 13-1
OSC RC
CROSS REFERENCE OF DEVICE SPECS (PIC16C72) FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C72-10 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 10 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 10 MHz max. Not recommended for use in LP mode PIC16C72-20 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. Not recommended for use in LP mode VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. Not recommended for use in HS mode PIC16LC72-04 VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. JW Devices VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max.
PIC16C72-04 VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max.
XT
HS
LP
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
TABLE 13-2
OSC RC
CROSS REFERENCE OF DEVICE SPECS (PIC16CR72) FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16CR72-10 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 10 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 10 MHz max. Not recommended for use in LP mode PIC16CR72-20 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. Not recommended for use in LP mode VDD: 2.5V to 5.5V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. Not recommended for use in HS mode PIC16LCR72-04 VDD: 2.5V to 5.5V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. VDD: 2.5V to 5.5V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. JW Devices VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 2.5V to 5.5V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max.
PIC16CR72-04 VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. VDD: 4.0V to 5.5V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max.
XT
HS
LP
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
DS39016A-page 78
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
13.1 DC Characteristics: PIC16C72/CR72-04 (Commercial, Industrial, Extended) PIC16C72/CR72-10 (Commercial, Industrial, Extended) PIC16C72/CR72-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial Sym VDD VDR VPOR PIC16C72 Min 4.0 4.5 Typ 1.5 VSS Max 6.0 5.5 Min 4.0 4.5 PIC16CR72 Typ 1.5 VSS Max 5.5 5.5 Units V V V V See section on Poweron Reset for details See section on Poweron Reset for details BODEN bit in configuration word enabled Extended Only XT, RC osc FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc FOSC = 20 MHz, VDD = 5.5V BOR enabled, VDD = 5.0V VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +125C BOR enabled VDD = 5.0V Conditions XT, RC and LP osc HS osc
DC CHARACTERISTICS
Param No. D001 D001A D002* D003
Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Poweron Reset Signal VDD rise rate to ensure internal Power-on Reset Signal Brown-out Reset Voltage
D004*
SVDD
0.05
-
-
0.05
-
-
V/ms
D005
Bvdd
3.7 3.7
4.0 4.0 2.7
4.3 4.4 5.0
3.7 3.7 -
4.0 4.0 2.7
4.3 4.4 5.0
V V mA
D010
Supply Current (Note 2,5)
IDD
-
D013
-
10
20
-
10
20
mA
D015 D020 D021 D021A D021B D023 * Note 1: Note 2:
Brown-out Reset Current (Note 6) Power-down Current (Note 3,5)
Ibor IPD
-
350 10.5 1.5 1.5 2.5 350
425 42 16 19 19 425
-
350 10.5 1.5 1.5 2.5 350
425 42 16 19 19 425
A A A A A A
Brown-out Reset Current (Note 6)
Ibor
-
Note 3: Note 4: Note 5: Note 6:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 79
PIC16C72 Series
13.2 DC Characteristics: PIC16LC72/LCR72-04 (Commercial, Industrial)
DC CHARACTERISTICS Param No. D001 D002* D003 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Sym VDD VDR VPOR PIC16C72 Min 2.5 Typ 1.5 VSS Max 6.0 Min 2.5 PIC16CR72 Typ 1.5 VSS Max 5.5 Units V V V See section on Poweron Reset for details See section on Poweron Reset for details BODEN bit in configuration word enabled XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled BOR enabled VDD = 5.0V VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C BOR enabled VDD = 5.0V Conditions LP, XT, RC (DC - 4 MHz)
Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Poweron Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2,5)
D004*
SVDD
0.05
-
-
0.05
-
-
V/ms
D005 D010
Bvdd IDD
3.7 -
4.0 2.0
4.3 3.8
3.7 -
4.0 2.0
4.3 3.8
V mA
D010A
-
22.5
48
-
22.5
48
A
D015* D020 D021 D021A D023* * Note 1: Note 2:
Brown-out Reset Current (Note 6) Power-down Current (Note 3,5)
Ibor IPD
-
350 7.5 0.9 0.9 350
425 30 5 5 425
-
350 7.5 0.9 0.9 350
425 30 5 5 425
A A A A A
Brown-out Reset Current (Note 6)
Ibor
-
Note 3: Note 4: Note 5: Note 6:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
DS39016A-page 80
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
13.3 DC Characteristics: PIC16C72/CR72-04 (Commercial, Industrial, Extended) PIC16C72/CR72-10 (Commercial, Industrial, Extended) PIC16C72/CR72-20 (Commercial, Industrial, Extended) PIC16LC72/LCR72-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Sym Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No.
Characteristic Input Low Voltage I/O ports
VIL VSS Vss VSS VSS VSS VIH 2.0 0.25VDD + 0.8V 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5 VDD 5.5V
D030 D030A D031 D032 D033
with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer
Note1
D040 D040A
VDD VDD
V V
4.5 VDD 5.5V For entire VDD range
D041 D042 D042A D043 D070 D060 D061 D063
with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports MCLR, RA4/T0CKI OSC1 Output Low Voltage I/O ports IPURB IIL
0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 -
250 -
VDD VDD Vdd VDD 400 1 5 5
V V V V A A A A
For entire VDD range Note1 VDD = 5V, VPIN = VSS Vss VPIN VDD, Pin at hiimpedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C
D080 D080A D083 D083A * Note 1: Note 2: Note 3:
VOL
-
-
0.6 0.6 0.6 0.6
V V V V
OSC2/CLKOUT (RC osc config)
-
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 81
PIC16C72 Series
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Sym Min Typ Max Units Conditions
Param No. D090 D090A D092 D092A D150*
Characteristic Output High Voltage I/O ports (Note 3)
VOH
VDD - 0.7 VDD - 0.7
-
14 TBD
V V V V V V
IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin, PIC16C72/LC72 RA4 pin, PIC16CR72/LCR72
OSC2/CLKOUT (RC osc config)
VDD - 0.7 VDD - 0.7
Open-Drain High Voltage Capacitive Loading Specs on Output Pins OSC2 pin
Vod
-
D100
COSC2
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101 D102 * Note 1: Note 2: Note 3:
All I/O pins and OSC2 (in RC mode) SCL, SDA in I2C mode
CIO Cb
-
-
50 400
pF pF
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin.
DS39016A-page 82
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
13.4 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS 2. TppS T F pp cc ck cs di do dt io mc S F H I L I2C only AA BUF CC HD ST DAT STA DATA input hold START condition STO STOP condition Hold SU Setup output access Bus free High Low High Low Fall High Invalid (Hi-impedance) Low P R V Z Period Rise Valid Hi-impedance CCP1 CLKOUT CS SDI SDO Data in I/O port MCLR osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR Frequency T Time Lowercase letters (pp) and their meanings: 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only)
Uppercase letters and their meanings:
TCC:ST (I2C specifications only)
FIGURE 13-1: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 83
PIC16C72 Series
13.5 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 2 3 3 4 4
CLKOUT
TABLE 13-3
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym Fosc Characteristic External CLKIN Frequency (Note 1) Min DC DC DC DC Oscillator Frequency (Note 1) DC DC 0.1 4 5 250 250 100 50 5 250 250 250 100 50 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 4 4 10 20 200 4 4 20 200 -- -- -- -- -- -- 10,000 250 250 250 -- DC -- -- -- 25 50 15 Units MHz MHz MHz MHz kHz MHz MHz MHz kHz ns ns ns ns s ns ns ns ns ns s ns ns s ns ns ns ns Conditions XT and RC osc mode HS osc mode (-04) HS osc mode (-10) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode XT and RC osc mode HS osc mode (-04) HS osc mode (-10) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode (-04) HS osc mode (-10) HS osc mode (-20) LP osc mode TCY = 4/FOSC XT oscillator LP oscillator HS oscillator XT oscillator LP oscillator HS oscillator
1
Tosc
External CLKIN Period (Note 1)
Oscillator Period (Note 1)
2 3
TCY TosL, TosH TosR, TosF
Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time
5 200 100 2.5 15 -- -- --
4
Note 1:
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS39016A-page 84
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
FIGURE 13-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21 Note: Refer to Figure 13-1 for load conditions. 15 new value 19 18 12 16 11 Q1 Q2 Q3
TABLE 13-4
Parameter No. 10* 11* 12* 13* 14* 15* 16* 17* 18*
CLKOUT AND I/O TIMING REQUIREMENTS
Sym Characteristic OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16C72/CR72 PIC16LC72/LCR72 Min -- -- -- -- -- TOSC + 200 0 -- 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5TCY + 20 -- -- 150 -- -- -- 40 80 40 80 -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI
19* 20* 21* 22* 23* * Note 1:
TioV2osH TioR TioF Tinp Trbp
Port input valid to OSC1 (I/O in setup time) PIC16C72/CR72 PIC16LC72/LCR72 PIC16C72/CR72 PIC16LC72/LCR72
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 85
PIC16C72 Series
FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins 32 30
31 34
Note: Refer to Figure 13-1 for load conditions.
FIGURE 13-5: BROWN-OUT RESET TIMING
VDD
BVDD 35
TABLE 13-5
Parameter No. 30 31* 32 33* 34 35 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ TBOR Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset pulse width Min 2 7 -- 28 -- 100 Typ -- 18 1024TOSC 72 -- -- Max -- 33 -- 132 2.1 -- Units s ms -- ms s s VDD BVDD (D005) Conditions VDD = 5V, -40C to +125C VDD = 5V, -40C to +125C TOSC = OSC1 period VDD = 5V, -40C to +125C
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS39016A-page 86
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
FIGURE 13-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
40 42 RC0/T1OSO/T1CKI
41
45 47 TMR0 or TMR1
Note: Refer to Figure 13-1 for load conditions.
46 48
TABLE 13-6
Param No.
40* 41* 42*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5TCY + 20 15 25 30 50 0.5TCY + 20 15 25 30 50 Greater of: 30 OR TCY + 40 N Greater of: 50 OR TCY + 40 N 60 100 DC Typ Max Units -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47
Sym Tt0H Tt0L Tt0P
45*
Tt1H
46*
Tt1L
47*
Tt1P
T1CKI High Time Synchronous, Prescaler = 1 Synchronous, PIC16C7X/CR72 Prescaler = PIC16LC7X/LCR72 2,4,8 Asynchronous PIC16C7X/CR72 PIC16LC7X/LCR72 T1CKI Low Time Synchronous, Prescaler = 1 Synchronous, PIC16C7X/CR72 Prescaler = PIC16LC7X/LCR72 2,4,8 Asynchronous PIC16C7X/CR72 PIC16LC7X/LCR72 T1CKI input Synchronous PIC16C7X/CR72 period PIC16LC7X/LCR72
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns
Must also meet parameter 47
N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8)
48 *
Asynchronous PIC16C7X/CR72 -- -- ns PIC16LC7X/LCR72 -- -- ns Ft1 Timer1 oscillator input frequency range -- 200 kHz (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc -- 7Tosc -- These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 87
PIC16C72 Series
FIGURE 13-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1)
RC2/CCP1 (Capture Mode) 50 52 51
RC2/CCP1 (Compare or PWM Mode) 53 54
Note: Refer to Figure 13-1 for load conditions.
TABLE 13-7
Param No. 50* Sym TccL
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Characteristic CCP1 input low time No Prescaler With Prescaler PIC16C72/CR72 PIC16LC72/LCR72 Min 0.5TCY + 20 10 20 0.5TCY + 20 10 20 3TCY + 40 N PIC16C72/CR72 PIC16LC72/LCR72 -- -- -- -- Typ Max Units -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 45 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4 or 16) Conditions
51*
TccH CCP1 input high time No Prescaler With Prescaler PIC16C72/CR72 PIC16LC72/LCR72
52* 53*
TccP
CCP1 input period
TccR CCP1 output rise time
54*
TccF
CCP1 output fall time
PIC16C72/CR72 PIC16LC72/LCR72
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS39016A-page 88
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
FIGURE 13-8: SPI MASTER OPERATION TIMING (CKE = 0)
SS 70 SCK (CKP = 0) 71 72
78
79
SCK (CKP = 1) 79 78
80 SDO MSB 75, 76 SDI MSB IN 74 73 Refer to Figure 13-1 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSB
LSB IN
FIGURE 13-9: SPI MASTER OPERATION TIMING (CKE = 1)
SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
SDO
MSB 75, 76
BIT6 - - - - - -1
LSB
SDI
MSB IN 74
BIT6 - - - -1
LSB IN
Refer to Figure 13-1 for load conditions.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 89
PIC16C72 Series
FIGURE 13-10: SPI SLAVE MODE TIMING (CKE = 0)
SS 70 SCK (CKP = 0) 71 72 83
78
79
SCK (CKP = 1) 79 78
80 SDO MSB 75, 76 SDI MSB IN 74 73 Refer to Figure 13-1 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSB 77 LSB IN
FIGURE 13-11: SPI SLAVE MODE TIMING (CKE = 1)
82 SS
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSB 75, 76
BIT6 - - - - - -1
LSB 77
SDI
MSB IN 74
BIT6 - - - -1
LSB IN
Refer to Figure 13-1 for load conditions.
DS39016A-page 90
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
TABLE 13-8
Param No. 70 71 72 73 74 75 76 77 78 79 80 Sym TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscH2doV, TscL2doV
SPI SLAVE MODE REQUIREMENTS (CKE=0) - PIC16C72
Characteristic SS to SCK or SCK input SCK input high time (slave mode) SCK input low time (slave mode) Setup time of SDI data input to SCK edge Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (master mode) SCK output fall time (master mode) SDO data output valid after SCK edge Min TCY TCY + 20 TCY + 20 50 50 -- -- 10 -- -- -- Typ -- -- -- -- -- 10 10 -- 10 10 -- Max -- -- -- -- -- 25 25 50 25 25 50 Units ns ns ns ns ns ns ns ns ns ns ns Conditions
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 13-9
Parameter No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83*
SPI MODE REQUIREMENTS - PIC16CR72
Sym TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscH2doV, TscL2doV TdoV2scH, TdoV2scL TssL2doV Characteristic SS to SCK or SCK input SCK input high time (slave mode) SCK input low time (slave mode) Setup time of SDI data input to SCK edge Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (master mode) SCK output fall time (master mode) SDO data output valid after SCK edge SDO data output setup to SCK edge SDO data output valid after SS edge SS after SCK edge Min TCY TCY + 20 TCY + 20 100 100 -- -- 10 -- -- -- TCY -- Typ -- -- -- -- -- 10 10 -- 10 10 -- -- -- Max -- -- -- -- -- 25 25 50 25 25 50 -- 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions
*
1.5TCY + 40 -- -- ns TscH2ssH, TscL2ssH These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 91
PIC16C72 Series
FIGURE 13-12: I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition Note: Refer to Figure 13-1 for load conditions
STOP Condition
TABLE 13-10
Parameter No. 90 91 92 93
I2C BUS START/STOP BITS REQUIREMENTS
Sym Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for repeated START condition After this period the first clock pulse is generated
TSU:STA THD:STA TSU:STO THD:STO
DS39016A-page 92
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
FIGURE 13-13: I2C BUS DATA TIMING
103 100 101 102
SCL
90 91 106 107 92
SDA In
110 109 109
SDA Out Note: Refer to Figure 13-1 for load conditions
TABLE 13-11
Parameter No. 100
I2C BUS DATA REQUIREMENTS
Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module Min 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1Cb -- 20 + 0.1Cb 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start Note 1 Note 2 Cb is specified to be from 10 to 400 pF Only relevant for repeated START condition After this period the first clock pulse is generated Cb is specified to be from 10 to 400 pF s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Units s s Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
Sym THIGH
101
TLOW
Clock low time
100 kHz mode 400 kHz mode SSP Module
102
TR
SDA and SCL rise time
100 kHz mode 400 kHz mode
103
TF
SDA and SCL fall time 100 kHz mode 400 kHz mode
90 91 106 107 92 109 110
TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
START condition setup time
100 kHz mode 400 kHz mode
START condition hold 100 kHz mode time 400 kHz mode Data input hold time Data input setup time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode STOP condition setup 100 kHz mode time 400 kHz mode Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
Cb Note 1: Note 2:
Bus capacitive loading
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz)S I2C-bus system, but the requirement tsu;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 93
PIC16C72 Series
TABLE 13-12 A/D CONVERTER CHARACTERISTICS: PIC16C72/CR72-04 (Commercial, Industrial, Extended) PIC16C72/CR72-10 (Commercial, Industrial, Extended) PIC16C72/CR72-20 (Commercial, Industrial, Extended) PIC16LC72/LCR72-04 (Commercial, Industrial)
Characteristic Resolution Total Absolute error Integral linearity error Differential linearity error Full scale error Offset error Monotonicity Reference voltage Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD) PIC16C72/CR72 PIC16LC72/LCR72 Min -- -- -- -- -- -- -- 2.5V VSS - 0.3 -- -- -- 10 Typ -- -- -- -- -- -- guaranteed -- -- -- 180 90 -- Max 8 bits <1 <1 <1 <1 <1 -- VDD + 0.3 VREF + 0.3 10.0 -- -- 1000 Units bit LSb LSb LSb LSb LSb -- V V k A A A Average current consumption when A/D is on. (Note 1) During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 9.1. During A/D Conversion cycle Conditions VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VSS VAIN VREF
Param No. A01 A02 A03 A04 A05 A06 A10 A20 A25 A30 A40
Sym NR EABS EIL EDL EFS EOFF -- VREF VAIN ZAIN IAD
A50
IREF
VREF input current (Note 2)
-- * Note 1: Note 2:
--
10
A
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
DS39016A-page 94
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
FIGURE 13-14: A/D CONVERSION TIMING
BSF ADCON0, GO 134 Q4 130 A/D CLK 132 (TOSC/2) (1) 131
1 TCY
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
SAMPLE
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 13-13
Param No. 130 Sym TAD
A/D CONVERSION REQUIREMENTS
Characteristic A/D clock period PIC16C72/LCR72 PIC16LC72/LCR72 PIC16C72/LCR72 PIC16LC72/LCR72 Min 1.6 2.0 2.0 2.5 -- Note 2 5* Typ -- -- 4.0 6.0 9.5 20 -- Max -- -- 6.0 9.0 -- -- -- Units s s s s TAD s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 2.5V TOSC based, VREF full range A/D RC Mode A/D RC Mode
131 132
TCNV TACQ
Conversion time (not including S/H time) (Note 1) Acquisition time
134
Tgo
Q4 to A/D clock start
--
TOSC/2
--
--
135 * Note 1: Note 2:
Tswc
Switching from convert sample time
1.5
--
--
TAD
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design. ADRES register may be read on the following TCY cycle. See Section 9.1 for min conditions.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 95
PIC16C72 Series
NOTES:
DS39016A-page 96
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72
14.0
PIC16C72 Series
DC AND AC CHARACTERISTICS GRAPHS AND TABLES - PIC16C72
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25C, while 'max' or 'min' represents (mean + 3) and (mean - 3) respectively, where is standard deviation.
FIGURE 14-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE)
35
30
25
IPD (nA)
20
15
10
5
0 2.5
3.0
3.5
4.0 4.5 VDD (Volts)
5.0
5.5
6.0
FIGURE 14-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE)
10.000 85C 70C 1.000
IPD (A)
0.100
25C
0C -40C 0.010
0.001 2.5
3.0
3.5
4.0 4.5 VDD (Volts)
5.0
5.5
6.0
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 97
PIC16C72 Series
PIC16C72
FIGURE 14-5: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
6.0 Cext = 22 pF, T = 25C 5.5 5.0 4.5 Fosc (MHz) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 R = 100k 0.5 0.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 R = 10k
FIGURE 14-3: TYPICAL IPD vs. VDD @ 25C (WDT ENABLED, RC MODE)
25 20 IPD (A)
R = 5k
15 10 5 0 2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
Shaded area is beyond recommended range.
FIGURE 14-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE)
35 30 25 IPD (A) 20 15 10 5 0 2.5 85C Fosc (MHz) 70C -40C 0C
FIGURE 14-6: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 R = 10k R = 5k R = 3.3k Cext = 100 pF, T = 25C
Data based on matrix samples. See first page of this section for details.
3.0
3.5
4.0
4.5
5.0
5.5
6.0
R = 100k
VDD (Volts)
5.5
6.0
VDD (Volts)
FIGURE 14-7: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
Cext = 300 pF, T = 25C 1000 900 800 Fosc (kHz) 700 600 500 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 R = 100k 5.5 6.0 R = 10k R = 5k R = 3.3k
VDD (Volts)
DS39016A-page 98
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72
FIGURE 14-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC MODE)
1400 1200 1000 IPD (A) 800 600 400 200 0 2.5 Device in Brown-out Reset 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 Device NOT in Brown-out Reset IPD (A) 30 25 20 15 10 5 0 2.5
PIC16C72 Series
FIGURE 14-10: TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE)
The shaded region represents the built-in hysteresis of the brown-out reset circuitry.
3.0
3.5
4.0 4.5 VDD (Volts)
5.0
5.5
6.0
FIGURE 14-9: MAXIMUM IPD vs. VDD BROWN-OUT DETECT ENABLED (85C TO -40C, RC MODE)
1600 1400 1200 IPD (A) 1000 800 600 400 200 4.3 0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 Device in Brown-out Reset Device NOT in Brown-out Reset
FIGURE 14-11: MAXIMUM IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C TO -40C, RC MODE)
45 40 35 30 IPD (A) 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
The shaded region represents the built-in hysteresis of the brown-out reset circuitry.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 99
Data based on matrix samples. See first page of this section for details.
PIC16C72 Series
2000 1800 1600 1400 IDD (A) 1200 1000 800 600 400 200 0 0.0
PIC16C72
FIGURE 14-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25C)
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Frequency (MHz)
Shaded area is beyond recommended range
FIGURE 14-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40C TO 85C)
2000 1800 1600 1400 IDD (A) 1200 1000 800 600 400 200 0 0.0
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
Data based on matrix samples. See first page of this section for details.
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Frequency (MHz)
Shaded area is beyond recommended range
DS39016A-page 100
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72
PIC16C72 Series
FIGURE 14-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25C)
1600
6.0V
1400
5.5V 5.0V
1200
4.5V 4.0V
1000
3.5V
IDD (A)
800
3.0V
2.5V
600
400
200
0 0 200 400 Shaded area is beyond recommended range 600 800 1000 1200 1400 1600 1800 Frequency (kHz)
FIGURE 14-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40C TO 85C)
1600
6.0V
1400
5.5V 5.0V
1200
4.5V 4.0V
1000
3.5V
800
3.0V
2.5V
600
400
200
0 0 200 400 600 800 1000 1200 1400 1600 1800 Shaded area is beyond recommended range Frequency (kHz)
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 101
Data based on matrix samples. See first page of this section for details.
IDD (A)
PIC16C72 Series
1200
PIC16C72
FIGURE 14-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25C)
6.0V 5.5V
1000
5.0V 4.5V
800
4.0V 3.5V
IDD (A)
3.0V
600
2.5V
400
200
0 0 100 200 300 400 500 600 700 Frequency (kHz)
FIGURE 14-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40C TO 85C)
1200
6.0V 5.5V
1000
5.0V 4.5V
Data based on matrix samples. See first page of this section for details.
800
4.0V 3.5V
IDD (A)
3.0V
600
2.5V
400
200
0 0 100 200 300 400 500 600 700 Frequency (kHz)
DS39016A-page 102
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72
FIGURE 14-18: TYPICAL IDD vs. CAPACITANCE @ 500 kHz (RC MODE)
600 3.5 500 400 IDD (A) 300 200 100 0 20 pF 5.0V 3.0 gm (mA/V) 4.0V 3.0V 2.5 2.0 1.5 1.0 0.5 0.0 3.0 100 pF Capacitance (pF) 300 pF
PIC16C72 Series
FIGURE 14-19: TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD
4.0 Max -40C
Typ 25C
Min 85C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts) Shaded area is beyond recommended range
TABLE 14-1
RC OSCILLATOR FREQUENCIES
Average Rext Fosc @ 5V, 25C 5k 10k 100k 4.12 MHz 2.35 MHz 268 kHz 1.80 MHz 1.27 MHz 688 kHz 77.2 kHz 707 kHz 501 kHz 269 kHz 28.3 kHz 1.4% 1.4% 1.1% 1.0% 1.0% 1.2% 1.0% 1.4% 1.2% 1.6% 1.1%
FIGURE 14-20: TRANSCONDUCTANCE(gm) OF LP OSCILLATOR vs. VDD
110 100 90 80 gm (A/V) 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Min 85C Typ 25C Max -40C
Cext 22 pF
100 pF
3.3k 5k 10k 100k
300 pF
3.3k 5k 10k 100k
VDD (Volts) Shaded areas are beyond recommended range
The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V.
FIGURE 14-21: TRANSCONDUCTANCE(gm) OF XT OSCILLATOR vs. VDD
1000 900 800 700 gm (A/V) 600 500 400 300 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD (Volts) Shaded areas are beyond recommended range 7.0 Min 85C Typ 25C Max -40C
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 103
Data based on matrix samples. See first page of this section for details.
PIC16C72 Series
PIC16C72
FIGURE 14-24: TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25C)
FIGURE 14-22: TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25C)
3.5 3.0 Startup Time (Seconds) 2.5
70 60 50
2.0
32 kHz, 33 pF/33 pF
Startup Time (ms)
40
200 kHz, 68 pF/68 pF
1.5 1.0 0.5 0.0 2.5
200 kHz, 15 pF/15 pF
30
200 kHz, 47 pF/47 pF
20
1 MHz, 15 pF/15 pF
10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
4 MHz, 15 pF/15 pF
3.0
3.5
4.0 4.5 VDD (Volts)
5.0
5.5
6.0
VDD (Volts)
FIGURE 14-23: TYPICAL XTAL STARTUP TIME vs. VDD (HS MODE, 25C)
7 6 Startup Time (ms) 5 4
8 MHz, 33 pF/33 pF 20 MHz, 33 pF/33 pF
TABLE 14-2
CAPACITOR SELECTION FOR CRYSTAL OSCILLATORS
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
Osc Type LP XT
3 2 1 4.0
20 MHz, 15 pF/15 pF 8 MHz, 15 pF/15 pF
HS
4 MHz 8 MHz 20 MHz
Data based on matrix samples. See first page of this section for details.
4.5
5.0 VDD(Volts)
5.5
6.0 Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM
DS39016A-page 104
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72
FIGURE 14-25: TYPICAL IDD vs. FREQUENCY (LP MODE, 25C)
PIC16C72 Series
FIGURE 14-27: TYPICAL IDD vs. FREQUENCY (XT MODE, 25C)
1800 1600
6.0V 5.5V 5.0V 4.5V
120 1400 100 1200 80 IDD (A) 1000 60 40 20 0 0
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
4.0V 3.5V 3.0V
IDD (A)
800 600 400
2.5V
50
100 Frequency (kHz)
150
200
200 0 0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
Frequency (MHz)
FIGURE 14-26: MAXIMUM IDD vs. FREQUENCY (LP MODE, 85C TO -40C)
140 120 100 IDD (A) 80 60 40 20 0 0
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
FIGURE 14-28: MAXIMUM IDD vs. FREQUENCY (XT MODE, -40C TO 85C)
1800 1600 1400 1200 1000 IDD (A) 800 600 400 200
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
50
100 Frequency (kHz)
150
200 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Frequency (MHz)
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 105
Data based on matrix samples. See first page of this section for details.
PIC16C72 Series
PIC16C72
FIGURE 14-30: MAXIMUM IDD vs. FREQUENCY (HS MODE, -40C TO 85C)
7.0
FIGURE 14-29: TYPICAL IDD vs. FREQUENCY (HS MODE, 25C)
7.0 6.0
6.0 5.0 5.0 IDD(mA) 4.0 3.0 2.0 1.0 0.0 12
6.0V 5.5V 5.0V 4.5V 4.0V
IDD (mA)
4.0 3.0 2.0 1.0
6.0V 5.5V 5.0V 4.5V 4.0V
4
6
8
10
12
14
16
18
20
Frequency (MHz)
0.0 12
4
6
8
10
12
14
16
18
20
Frequency (MHz)
TABLE 14-3
Process Technology
TYPICAL EPROM ERASE TIME RECOMMENDATIONS
Wavelength (Angstroms) Intensity (W/ cm2) Distance from UV lamp (inches) 1 1 1 1 Typical Time (1) (minutes) 15 - 20 20 40 60
57K 2537 12,000 77K 2537 12,000 90K 2537 12,000 120K 2537 12,000 Note 1: If these criteria are not met, the erase times will be different.
Data based on matrix samples. See first page of this section for details.
Note:
Fluorescent lights and sunlight both emit ultraviolet light at the erasure wavelength. Leaving a UV erasable device's window uncovered could cause, over time, the devices memory cells to become erased. The erasure time for a fluorescent light is about three years. While sunlight requires only about one week. To prevent the memory cells from losing data an opaque label should be placed over the erasure window.
DS39016A-page 106
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CR72
15.0
PIC16C72 Series
DC AND AC CHARACTERISTICS GRAPHS AND TABLES - PIC16CR72
NO GRAPHS OR TABLES AVAILABLE AT THIS TIME
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 107
PIC16C72 Series
NOTES:
PIC16CR72
DS39016A-page 108
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
16.0
16.1
PACKAGING INFORMATION
Package Marking Information
28-Lead Side Brazed Skinny Windowed XXXXXXXXXXX XXXXXXXXXXX AABBCDE
Example PIC16C72/JW 9517CAT
28-Lead PDIP (Skinny DIP) MMMMMMMMMMMM XXXXXXXXXXXXXXX AABBCDE
Example PIC16C72-04/SP AABBCDE
28-Lead SOIC MMMMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXXXX AABBCDE
Example PIC16C72-04/SO 945/CAA
28-Lead SSOP
XXXXXXXXXXXX XXXXXXXXXXXX
Example
PIC16C72 20I/SS025
AABBCAE
9517SBP
Legend: MM...M XX...X AA BB C
D E
Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5" Line S = 6" Line H = 8" Line Mask revision number Assembly code of the plant or country of origin in which part was assembled
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 109
PIC16C72 Series
16.2 28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil)(JW)
E
W2
D
2 n W1 E1 A R eB c A2 B1 B p A1 L 1
Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Radius to Radius Width Overall Row Spacing Window Width Window Length * Controlling Parameter.
MIN n p B B1 R c A A1 A2 L D E E1 eB W1 W2
0.098 0.016 0.050 0.010 0.008 0.170 0.107 0.015 0.135 1.430 0.285 0.255 0.345 0.130 0.290
INCHES* NOM 0.300 28 0.100 0.019 0.058 0.013 0.010 0.183 0.125 0.023 0.140 1.458 0.290 0.270 0.385 0.140 0.300
MAX
MIN
0.102 0.021 0.065 0.015 0.012 0.195 0.143 0.030 0.145 1.485 0.295 0.285 0.425 0.150 0.310
MILLIMETERS NOM MAX 7.62 28 2.59 2.54 2.49 0.47 0.53 0.41 1.46 1.65 1.27 0.32 0.38 0.25 0.25 0.30 0.20 4.32 4.64 4.95 3.18 3.63 2.72 0.57 0.76 0.00 3.56 3.68 3.43 37.02 37.72 36.32 7.37 7.49 7.24 6.86 7.24 6.48 9.78 10.80 8.76 0.14 0.15 0.13 0.3 0.31 0.29
DS39016A-page 110
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
16.3 28-Lead Plastic Dual In-line (300 mil) (SP)
E
D
2 n E1 A R eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter.
1
A1
c A2 B1 B INCHES* NOM 0.300 28 0.100 0.019 0.016 0.053 0.040 0.005 0.000 0.010 0.008 0.150 0.140 0.090 0.070 0.020 0.015 0.130 0.125 1.365 1.345 0.288 0.280 0.270 0.283 0.320 0.350 5 10 5 10 p
L
MIN n p B B1 R c A A1 A2 L D E E1 eB
MAX
MIN
0.022 0.065 0.010 0.012 0.160 0.110 0.025 0.135 1.385 0.295 0.295 0.380 15 15
MILLIMETERS NOM MAX 7.62 28 2.54 0.48 0.41 0.56 1.33 1.02 1.65 0.13 0.00 0.25 0.25 0.20 0.30 3.81 3.56 4.06 2.29 1.78 2.79 0.51 0.38 0.64 3.30 3.18 3.43 34.67 34.16 35.18 7.11 7.30 7.49 7.49 6.86 7.18 8.13 8.89 9.65 5 10 15 5 10 15
Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 111
PIC16C72 Series
16.4 28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO)
E1 E p
D
B n X 45 c A L1 A2 INCHES* NOM 0.050 28 0.099 0.093 0.058 0.048 0.008 0.004 0.706 0.700 0.296 0.292 0.407 0.394 0.020 0.010 0.005 0.005 0.005 0.005 0.016 0.011 0 4 0.015 0.010 0.011 0.009 0.014 0.017 0 12 0 12 MILLIMETERS NOM MAX 1.27 28 2.36 2.50 2.64 1.22 1.47 1.73 0.10 0.19 0.28 17.93 17.78 18.08 7.42 7.51 7.59 10.01 10.33 10.64 0.50 0.25 0.74 0.13 0.13 0.25 0.13 0.13 0.25 0.28 0.41 0.53 8 0 4 0.25 0.38 0.51 0.23 0.27 0.30 0.36 0.42 0.48 0 12 15 0 12 15 A1 L R2 2 1
Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
R1
MIN p n A A1 A2 D E E1 X R1 R2 L L1 c B
MAX
MIN
0.104 0.068 0.011 0.712 0.299 0.419 0.029 0.010 0.010 0.021 8 0.020 0.012 0.019 15 15
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS39016A-page 112
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
16.5 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS)
E1 E p
D
B n 2 1 L c R2 A
A1 R1 L1 A2
Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
MIN p n A A1 A2 D E E1 R1 R2 L L1 c B
INCHES NOM 0.026 28 0.073 0.068 0.036 0.026 0.005 0.002 0.402 0.396 0.208 0.205 0.306 0.301 0.005 0.005 0.005 0.005 0.020 0.015 0 4 0.005 0.000 0.007 0.005 0.010 0.012 0 5 0 5
MAX
MIN
0.078 0.046 0.008 0.407 0.212 0.311 0.010 0.010 0.025 8 0.010 0.009 0.015 10 10
MILLIMETERS* NOM MAX 0.65 28 1.99 1.73 1.86 1.17 0.66 0.91 0.21 0.05 0.13 10.33 10.07 10.20 5.38 5.20 5.29 7.90 7.65 7.78 0.25 0.13 0.13 0.25 0.13 0.13 0.64 0.38 0.51 0 4 8 0.25 0.00 0.13 0.22 0.13 0.18 0.38 0.25 0.32 10 0 5 10 0 5
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 113
PIC16C72 Series
NOTES:
DS39016A-page 114
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
APPENDIX A: WHAT'S NEW IN THIS DATA SHEET
This is a new data sheet. However, information on the PIC16C72 device was previously found in the PIC16C7X Data Sheet, DS30390. Information on the PIC16CR72 device is new.
APPENDIX C: DEVICE DIFFERENCES
A table of the differences between the devices described in this document is found below. Difference SSP module in SPI mode PIC16C72 Basic SSP PIC16CR72 SSP
APPENDIX B: WHAT'S CHANGED IN THIS DATA SHEET
New data sheet.
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 115
PIC16C72 Series
NOTES:
DS39016A-page 116
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
INDEX
A
A/D ADCON0 Register ...................................................... 53 ADCON1 Register ...................................................... 54 ADIF bit ...................................................................... 55 Analog Input Model Block Diagram ............................ 56 Analog-to-Digital Converter ........................................ 53 Block Diagram ............................................................ 55 Configuring Analog Port Pins ..................................... 57 Configuring the Interrupt ............................................ 55 Configuring the Module .............................................. 55 Conversion Clock ....................................................... 57 Conversions ............................................................... 58 Converter Characteristics .......................................... 94 GO/DONE bit ............................................................. 55 Internal Sampling Switch (Rss) Impedance ............... 56 Sampling Requirements ............................................. 56 Source Impedance ..................................................... 56 Using the CCP Trigger ............................................... 58 Absolute Maximum Ratings ............................................... 77 ACK .............................................................................. 47, 49 ADIE bit .............................................................................. 12 ADIF bit .............................................................................. 13 ADRES Register ...................................................... 7, 53, 55 Application Notes AN546 (Using the Analog-to-Digital Converter) ......... 53 AN578 (Use of the SSP Module in the I2C Multi-Master Environment) ......................................... 39 Mode ................................................................. 34 Prescaler ........................................................... 34 CCP Timer Resources ............................................... 33 Compare Block Diagram ................................................... 35 Mode ................................................................. 35 Software Interrupt Mode .................................... 35 Special Event Trigger ........................................ 35 Special Trigger Output of CCP1 ........................ 35 Special Trigger Output of CCP2 ........................ 35 Section ....................................................................... 33 Special Event Trigger and A/D Conversions ............. 35 Capture/Compare/PWM (CCP) PWM Block Diagram ................................................. 36 PWM Mode ................................................................ 36 PWM, Example Frequencies/Resolutions ................. 37 CCP1IE bit ......................................................................... 12 CCP1IF bit ......................................................................... 13 CCPR1H Register ............................................................. 33 CCPR1L Register .............................................................. 33 CCPxM0 bit ....................................................................... 33 CCPxM1 bit ....................................................................... 33 CCPxM2 bit ....................................................................... 33 CCPxM3 bit ....................................................................... 33 CCPxX bit .......................................................................... 33 CCPxY bit .......................................................................... 33 CKE ................................................................................... 43 CKP ............................................................................. 41, 44 Clock Polarity Select bit, CKP ..................................... 41, 44 Code Examples Changing Between Capture Prescalers .................... 34 Initializing PORTA ..................................................... 19 Initializing PORTB ..................................................... 21 Initializing PORTC ..................................................... 23 Code Protection ........................................................... 59, 72 Configuration Bits .............................................................. 59
B
BF .......................................................................... 40, 43, 47 Block Diagrams A/D ............................................................................. 55 Analog Input Model .................................................... 56 Capture ...................................................................... 34 Compare .................................................................... 35 I2C Mode .................................................................... 47 On-Chip Reset Circuit ................................................ 62 PIC16C72 .................................................................... 3 PIC16CR72 .................................................................. 3 PORTC ...................................................................... 23 PWM .......................................................................... 36 RA3:RA0 and RA5 Port Pins ..................................... 19 RA4/T0CKI Pin ........................................................... 19 RB3:RB0 Port Pins .................................................... 21 RB7:RB4 Port Pins .................................................... 21 SSP in I2C Mode ........................................................ 47 SSP in SPI Mode ................................................. 42, 45 Timer0 ........................................................................ 25 Timer0/WDT Prescaler .............................................. 26 Timer2 ........................................................................ 31 Watchdog Timer ......................................................... 70 BOR bit ........................................................................ 14, 64 Buffer Full Status bit, BF .............................................. 40, 43
D
D/A ............................................................................... 40, 43 Data/Address bit, D/A .................................................. 40, 43 DC bit ....................................................................................9 DC Characteristics PIC16C72 .................................................................. 79 Development Support ........................................................ 75 Development Tools ............................................................ 75 Direct Addressing .............................................................. 17
E
Electrical Characteristics PIC16C72 .................................................................. 77 External Power-on Reset Circuit ....................................... 63
F
FSR Register ............................................................. 7, 8, 17 Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) ................... 75
G
GIE bit ................................................................................ 68
C
C bit ...................................................................................... 9 Capture/Compare/PWM Capture Block Diagram ................................................... 34 CCP1CON Register ........................................... 33 CCP1IF .............................................................. 34 CCPR1 ............................................................... 34 CCPR1H:CCPR1L ............................................. 34
I
I/O Ports PORTA ...................................................................... 19 PORTB ...................................................................... 21 PORTC ...................................................................... 23 Section ....................................................................... 19 I2C Addressing ................................................................. 48
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 117
PIC16C72 Series
Block Diagram ............................................................ 47 I2C Operation ............................................................. 47 Master Mode .............................................................. 51 Mode .......................................................................... 47 Mode Selection .......................................................... 47 Multi-Master Mode ..................................................... 51 Reception ................................................................... 49 Reception Timing Diagram ........................................ 49 SCL and SDA pins ..................................................... 47 Slave Mode ................................................................ 47 Transmission .............................................................. 50 In-Circuit Serial Programming ...................................... 59, 72 INDF Register ................................................................ 8, 17 Indirect Addressing ............................................................ 17 Initialization Condition for all Register ................................ 65 Instruction Format .............................................................. 73 Instruction Set Section ....................................................................... 73 Summary Table .......................................................... 74 INT Interrupt ....................................................................... 68 INTCON Register ............................................................... 11 INTEDG bit ................................................................... 10, 68 Internal Sampling Switch (Rss) Impedance ....................... 56 Interrupts ............................................................................ 59 PortB Change ............................................................ 68 RB7:RB4 Port Change ............................................... 21 Section ....................................................................... 68 TMR0 ......................................................................... 68 IRP bit .................................................................................. 9 PCFG0 bit .......................................................................... 54 PCFG1 bit .......................................................................... 54 PCFG2 bit .......................................................................... 54 PCL Register ............................................................. 7, 8, 15 PCLATH ............................................................................. 65 PCLATH Register ...................................................... 7, 8, 15 PCON Register ............................................................ 14, 64 PD bit ............................................................................. 9, 61 PICDEM-1 Low-Cost PIC16/17 Demo Board .................... 75 PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 75 PICMASTERTM RT In-Circuit Emulator .............................. 75 PICSTARTTM Low-Cost Development System ................... 75 PIE1 Register ..................................................................... 12 Pin Functions MCLR/Vpp ................................................................... 4 OSC1/CLKIN ............................................................... 4 OSC2/CLKOUT ........................................................... 4 RA0/AN0 ...................................................................... 4 RA1/AN1 ...................................................................... 4 RA2/AN2 ...................................................................... 4 RA3/AN3/Vref .............................................................. 4 RA4/T0CKI .................................................................. 4 RA5/AN4/SS ................................................................ 4 RB0/INT ....................................................................... 4 RB1 .............................................................................. 4 RB2 .............................................................................. 4 RB3 .............................................................................. 4 RB4 .............................................................................. 4 RB5 .............................................................................. 4 RB6 .............................................................................. 4 RB7 .............................................................................. 4 RC0/T1OSO/T1CKI ..................................................... 4 RC1/T1OSI .................................................................. 4 RC2/CCP1 ................................................................... 4 RC3/SCK/SCL ............................................................. 4 RC4/SDI/SDA .............................................................. 4 RC5/SDO ..................................................................... 4 RC6 ............................................................................. 4 RC7 ............................................................................. 4 SCK ..................................................................... 42-?? SDI ....................................................................... 42-?? SDO ..................................................................... 42-?? SS ........................................................................ 42-?? Vdd .............................................................................. 4 Vss ............................................................................... 4 Pinout Descriptions PIC16C72 .................................................................... 4 PIC16CR72 ................................................................. 4 PIR1 Register .................................................................... 13 POR ............................................................................. 63, 64 Oscillator Start-up Timer (OST) ........................... 59, 63 Power Control Register (PCON) ................................ 64 Power-on Reset (POR) ........................................ 59, 65 Power-up Timer (PWRT) ........................................... 59 Power-Up-Timer (PWRT) .......................................... 63 Time-out Sequence ................................................... 64 TO .............................................................................. 61 POR bit ........................................................................ 14, 64 Port RB Interrupt ................................................................ 68 PORTA .............................................................................. 65 PORTA Register ............................................................ 7, 19 PORTB .............................................................................. 65 PORTB Register ............................................................ 7, 21 PORTC .............................................................................. 65 PORTC Register ............................................................ 7, 23 Power-down Mode (SLEEP) .............................................. 71
L
Loading of PC .................................................................... 15
M
MCLR ........................................................................... 61, 64 Memory Data Memory ............................................................... 6 Program Memory ......................................................... 5 Program Memory Maps PIC16C72 ............................................................ 5 PIC16CR72 .......................................................... 5 Register File Maps PIC16C72 ............................................................ 6 PIC16CR72 .......................................................... 6 MPASM Assembler ............................................................ 75 MPSIM Software Simulator ................................................ 75
O
OPCODE ............................................................................ 73 OPTION Register ............................................................... 10 OSC selection .................................................................... 59 Oscillator HS ........................................................................ 60, 64 LP ......................................................................... 60, 64 RC .............................................................................. 60 XT ........................................................................ 60, 64 Oscillator Configurations .................................................... 60 Output of TMR2 .................................................................. 31
P
P ................................................................................... 40, 43 Packaging 28-Lead Ceramic w/Window .................................... 110 28-Lead PDIP .......................................................... 111 28-Lead SOIC .......................................................... 112 28-Lead SSOP ......................................................... 113 Paging, Program Memory .................................................. 16
DS39016A-page 118
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
PR2 Register ...................................................................... 31 Prescaler, Switching Between Timer0 and WDT ............... 26 PRO MATETM Universal Programmer ................................ 75 Program Memory Paging ........................................................................ 16 Program Memory Maps PIC16C72 .................................................................... 5 PIC16CR72 .................................................................. 5 Program Verification .......................................................... 72 PS0 bit ............................................................................... 10 PS1 bit ............................................................................... 10 PS2 bit ............................................................................... 10 PSA bit ............................................................................... 10 SPI Clock Edge Select bit, CKE ........................................ 43 SPI Data Input Sample Phase Select bit, SMP ................. 43 SPI Mode ........................................................................... 42 SS ...................................................................................... 42 SSP Module Overview ....................................................... 39 Section ....................................................................... 39 SSPCON ................................................................... 44 SSPSTAT .................................................................. 43 SSPADD Register ................................................................8 SSPCON ..................................................................... 41, 44 SSPEN ........................................................................ 41, 44 SSPIE bit ........................................................................... 12 SSPIF bit ........................................................................... 13 SSPM3:SSPM0 ........................................................... 41, 44 SSPOV .................................................................. 41, 44, 47 SSPSTAT .......................................................................... 40 SSPSTAT Register ........................................................ 8, 43 Stack .................................................................................. 16 Start bit, S .................................................................... 40, 43 STATUS Register .................................................................9 Stop bit, P .................................................................... 40, 43 Synchronous Serial Port (SSP) Block Diagram, SPI Mode ......................................... 42 SPI Mode ................................................................... 42 Synchronous Serial Port Enable bit, SSPEN ............... 41, 44 Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 ........................................................... 41, 44 Synchronous Serial Port Module ....................................... 39 Synchronous Serial Port Status Register .......................... 43
R
R/W .............................................................................. 40, 43 R/W bit ................................................................... 48, 49, 50 RBIF bit ........................................................................ 21, 68 RBPU bit ............................................................................ 10 RC Oscillator ................................................................ 61, 64 Read/Write bit Information, R/W .................................. 40, 43 Receive Overflow Detect bit, SSPOV ................................ 41 Receive Overflow Indicator bit, SSPOV ............................. 44 Register File ......................................................................... 6 Registers Initialization Conditions .............................................. 65 Maps PIC16C72 ............................................................ 6 PIC16CR72 .......................................................... 6 Reset Conditions ........................................................ 64 SSPCON Diagram ............................................................. 41 SSPSTAT ................................................................... 43 Diagram ............................................................. 40 Section ............................................................... 40 Reset ............................................................................ 59, 61 Reset Conditions for Special Registers ............................. 64 RP0 bit ............................................................................. 6, 9 RP1 bit ................................................................................. 9
T
T0CS bit ............................................................................. 10 T1CKPS0 bit ...................................................................... 27 T1CKPS1 bit ...................................................................... 27 T1CON Register ................................................................ 27 T1OSCEN bit ..................................................................... 27 T1SYNC bit ........................................................................ 27 T2CKPS0 bit ...................................................................... 32 T2CKPS1 bit ...................................................................... 32 T2CON Register ................................................................ 32 TAD .................................................................................... 57 Timer0 RTCC ......................................................................... 65 Timers Timer0 Block Diagram ................................................... 25 Interrupt ............................................................. 26 Prescaler ........................................................... 25 Prescaler Block Diagram ................................... 26 Section .............................................................. 25 Switching Prescaler Assignment ....................... 26 T0IF ................................................................... 68 TMR0 Interrupt .................................................. 68 Timer1 Capacitor Selection ........................................... 29 Oscillator ........................................................... 29 Resetting Timer1 using a CCP Trigger Output .. 29 T1CON .............................................................. 27 Timer2 Block Diagram ................................................... 31 Postscaler .......................................................... 31 Prescaler ........................................................... 31 T2CON .............................................................. 32
S
S ................................................................................... 40, 43 SCK .................................................................................... 42 SCL .................................................................................... 47 SDI ..................................................................................... 42 SDO ................................................................................... 42 Slave Mode SCL ............................................................................ 47 SDA ............................................................................ 47 SLEEP ......................................................................... 59, 61 SMP ................................................................................... 43 Special Event Trigger ......................................................... 58 Special Features of the CPU ............................................. 59 Special Function Registers PIC16C72 .................................................................... 7 PIC16CR72 .................................................................. 7 Special Function Registers, Section .................................... 7 SPI Block Diagram ...................................................... 42, 45 Mode .......................................................................... 42 Serial Clock ................................................................ 45 Serial Data In ............................................................. 45 Serial Data Out .......................................................... 45 Slave Select ............................................................... 45 SPI Mode ................................................................... 45 SSPCON .................................................................... 44 SSPSTAT ................................................................... 43
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 119
PIC16C72 Series
Timing Diagrams A/D Conversion .......................................................... 95 Brown-out Reset ........................................................ 86 Capture/Compare/PWM ............................................. 88 CLKOUT and I/O ........................................................ 85 External Clock Timing ................................................ 84 I2C Bus Data .............................................................. 93 I2C Bus Start/Stop bits ............................................... 92 I2C Reception (7-bit Address) .................................... 49 Power-up Timer ......................................................... 86 Reset .......................................................................... 86 Start-up Timer ............................................................ 86 Timer0 ........................................................................ 87 Timer1 ........................................................................ 87 Wake-up from Sleep via Interrupt .............................. 72 Watchdog Timer ......................................................... 86 TMR1CS bit ........................................................................ 27 TMR1H Register .................................................................. 7 TMR1IE bit ......................................................................... 12 TMR1IF bit ......................................................................... 13 TMR1L Register ................................................................... 7 TMR1ON bit ....................................................................... 27 TMR2 Register ..................................................................... 7 TMR2IE bit ......................................................................... 12 TMR2IF bit ......................................................................... 13 TMR2ON bit ....................................................................... 32 TO bit ................................................................................... 9 TOUTPS0 bit ...................................................................... 32 TOUTPS1 bit ...................................................................... 32 TOUTPS2 bit ...................................................................... 32 TOUTPS3 bit ...................................................................... 32 TRISA Register .............................................................. 8, 19 TRISB Register .............................................................. 8, 21 TRISC Register .............................................................. 8, 23
U
UA ................................................................................ 40, 43 Update Address bit, UA ................................................ 40, 43
W
Wake-up from SLEEP ........................................................ 71 Watchdog Timer (WDT) ................................... 59, 61, 64, 70 WCOL .......................................................................... 41, 44 WDT ................................................................................... 64 Block Diagram ............................................................ 70 Timeout ...................................................................... 65 Write Collision Detect bit, WCOL ................................. 41, 44
Z
Z bit ...................................................................................... 9
DS39016A-page 120
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
980106
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies.
(c) 1998 Microchip Technology Inc.
DS39016A-page 121
PIC16C72 Series
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C72 Series Questions: 1. What are the best features of this document? Y N Literature Number: DS39016A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS39016A-page 122
(c) 1998 Microchip Technology Inc.
PIC16C72 Series
PIC16C72 SERIES PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -XX X /XX Package XXX Pattern Examples:
f) PIC16C72 -04/P 301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. PIC16LC72 - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. PIC16CR72 - 10I/P = ROM program memory, Industrial temp., PDIP package, 10MHz, normal VDD limits.
Frequency Temperature Range Range
g) Device PIC16C72(1), PIC16C72T(2) PIC16LC72(1), PIC16LC72T(2) PIC16CR72(1), PIC16CR72T(2) PIC16LCR72(1), PIC16LCR72T(2) h)
Frequency Range
02 04 10 20 b(3) I E
= 2 MHz = 4 MHz = 10 MHz = 20 MHz
Note 1:
2: Temperature Range = 0C to 70C = -40C to +85C = -40C to +125C (Commercial) (Industrial) (Extended) 3:
C= CMOS CR= CMOS ROM LC= Low Power CMOS LCR= ROM Version, Extended Vdd range T = in tape and reel - SOIC, SSOP packages only. b = blank
Package
JW SO SP SS
= Ceramic Dual In-Line Package with Window = Small Outline - 300 mil = Skinny PDIP = Shrink Samll Outline Package - 209 mil
Pattern
3-digit Pattern Code for QTP, ROM (blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices).
SALES AND SUPPORT
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see last page) 2. 3. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Development Tools For the latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. The latest version of Development Tools software can be downloaded from either our Bulletin Board or Worldwide Web Site. (Information on how to connect to our BBS or WWW site can be found in the On-Line Support section of this data sheet.)
(c) 1998 Microchip Technology Inc.
Preliminary
DS39016A-page 123
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
ASIA/PACIFIC (CONTINUED)
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Dallas
Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 1/13/98
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338
Singapore
Microchip Technology Taiwan Singapore Branch 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 1998, Microchip Technology Incorporated, USA. 2/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS39016A-page 124
(c) 1998 Microchip Technology Inc.

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